 Wed Nov 25 02:52:35 2015, Chris Thompson, PC software beyond Windows 7
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I am new to this forum. I have ordered a DRS4 evaluation board for doing experiments with very fast PET detectors. It has not arrived yet. The version
of the manual I downloaded today shows software installation instructions for Windows 7 and earlier versions. I intend to use it on a 64bit PC running
Windows 8.1. Will the Windows 7 driver work, or is there an updated version for Windows 8 or 10? |
 Wed Nov 25 08:20:47 2015, Stefan Ritt, PC software beyond Windows 7
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Have a look here elog:434
Chris
Thompson wrote:
I am new to this forum. I have ordered a DRS4 evaluation board for |
Wed Nov 25 17:36:25 2015, Chris Thompson, PC software beyond Windows 7 
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I tried this suggestion of changing the startup settings to ingore driver license signing (as suggested in the post # 434), but when I tried to install
the software I got a error message which I captured from the screen and I have attached. Perhaps I have the wrong version, or, as suggested, the file I
downloaded from your site is incomplete? |
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Sat Dec 5 02:39:20 2015, Chris Thompson, PC software beyond Windows 7
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I tried restarting Windows 10 in a way the allowed me to use "advanced startup options" Option 7 suggested it was to restart without mandatory
driver signing. However, the error persists. Has anyone tested this latest version 5.0.4 on Windows 10? My hardware arrived today, and I am anxious to
test it.!!!! |
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Sat Dec 5 03:21:21 2015, Chris Thompson, PC software beyond Windows 7
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On a hunch, I tried downloading V 5.0.3 instead. This works, and I now have the oscilloscope mode displaying signals! (just to make sure, I re-tire version
5.0.4 and still get the same error. So, in summary V 5.0.3 seems to install successfully and work with Windows 10, but the newer V5.0.4 does not install...
I assmume that I am missing something though, as the newer version is 10 Mbytes bigger! |
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Tue Jan 12 12:57:46 2016, Stefan Ritt, PC software beyond Windows 7
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The 5.0.4 version was corrupt on our server. I fixed it, so now it shoudl also work fine (although there are only very minor changes between 5.0.3 and
5.0.4).
/Stefan |
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Thu Sep 29 17:26:13 2016, Jacob Hwang, Output Timing Drifting
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Hello,
I have designed four DRS4 chips (36 channels) on my board running at 1GHz (REFCLK=488.28KHz) and ROI mode. All 4 chips' REFCLK, DWRITE, RSRLOAD,
and SRCLK are buffer driven by the same source. SRCLK is set to 40MHz to reduce the readout time. |
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Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting
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Hi Jacob,
you are missing the timing calibration. Each sampling cell has not the same width. Running at 5 GSPS, cell widths scatter from 150 ps to 250
ps. If you integrate these widhts, you get a time scale which can be off by a few ns between chips, something you see in your plot. Here is a paper which |
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Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed
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Dear DRS4 team,
On page 3 of the data sheet, Table 1. for readout speed a typical value of 10 MHz is specified, but in the comment column it notes optimal performance
achieved at 33 MHz. |
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Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed
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The analog output of the DRS4 chip needs some time to settle. In principle it need an infinite amout of time (exponential curve) to settle to 100% of
the final value. So if we sample after a finite time, there is some error we do. Some of the error will be taken care of the voltage calibration, but there
remains some residual error depending on the value of the previous sampling cell. So all sampling speeds 10 MHz, 16 MHz, 33 MHz are kind of rule of thumbs. |
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Wed Feb 13 16:58:40 2013, Martin Petriska, Nonuniform sampling
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Are there any plans to include reconstruction of nonuniform sampling in DRS4 to get uniformly sampled data?
Im now reading article IEEE Trans on Circ. ans Systems I, Vol.55 No.8 sept. 2008 Reconstruction of Nonuniformly Sampled Bandlimited Signals Usinga
Differentiator–Multiplier Cascade by Stefan Tertinek and Christian Vogel |
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Wed Feb 13 17:03:53 2013, Stefan Ritt, Nonuniform sampling
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Martin Petriska wrote:
Are there any plans to include reconstruction of nonuniform sampling in DRS4 to get uniformly |
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Thu Mar 27 15:53:10 2025, Justin Tabbett, Noisy counts with adapted drs_exam.cpp
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Greetings,
I have adapted the drs_exam.cpp to allow for a user input number of channels and trigger levels.
The program mostly works well, however there are counts which form a noise peak, imposed on the regular channel response. |
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Thu Apr 28 15:47:53 2016, Stefan Ritt, New software version and binary format
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A new software version 5.0.5 has been released today. This fixes a few bugs in multi-board configurations, and adds saving of the scaler values into
XML and binary files. Please note that the binary file format has been changed for that. The new format is described in an updated manual (page
25), and reflected in a new read_binary.cpp program contained in the distribution. |
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Wed Jun 29 09:10:01 2016, Stefan Ritt, Negative input signals
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Hello everybody,
I get often asked if the DRS4 evaluation board can accomodate negative input pulses going to -1V. This is unfortunately not possible, since the
board is mainly for evaluation of the DRS4 chip and should not be seen as a complete oscilloscope with flexible input stage. So the maximum it can do is |
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Thu Apr 21 22:16:43 2016, Kyle Weinfurther, Negative fCellDT values from GetTimeCalibration()
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Hello Stefan,
I am using four DRS4 v5 eval boards to digitize 16 channels of data. I have recently changed from saving the timing information of the waveform
using GetTime() to GetTimeCalibration(). When changing over, I noticed that some values for fCellDT for cell 498 are negative. Over the 16 channels used, |
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Sat Apr 23 12:33:17 2016, Daniel Stricker-Shaver, Negative fCellDT values from GetTimeCalibration()
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Hi Kyle,
If I remember right the negative sampling width happens only for 498 and at high sampling speeds. It is described in a paper from Stefan:
http://arxiv.org/pdf/1405.4975.pdf |
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Tue Apr 26 09:54:16 2016, Stefan Ritt, Negative fCellDT values from GetTimeCalibration()
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I just realized that the negative bin widht is not explicitly mentioned in the quoted paper. So let me explain it here:
The negative value of cell 498 is correct and "real" in the sense that the signal is first captured in cell 498 and later
in cell 497. This is due to the exact layout of the cells on the chip and the input signal. Cell 498 is simply much closer to the input, so sees the |
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Thu Jun 28 19:55:45 2018, Woon-Seng Choong, Negative Bin Width
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I am using a DRS4 Evaluation Board v5 and running the drsosc.exe version 5.06 on a Window 7 machine. I have performed the voltage and timing calibration.
With test pulses on channel 1 and 2, I collected binary data file with all 4 channels active sampling at 5GSPS.
Attached is a distribution of the bin_width vs. cell # for all the 4 channels. Note that there are few cells with bin_width < 10 ps. |
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Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width
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Yes that's normal. A negative cell bin width means that the next cell N+1 samples the input signal before cell N. This can happen due to the signal
routing on the DRS4 chip.
Stefan |