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    Reply  Fri Mar 5 23:29:04 2010, Hao Huan, Readout of DRS Data 
Entry  Tue Mar 9 23:28:45 2010, Hao Huan, Serial Interface Frequency of the DRS Chip 
Entry  Thu Mar 11 21:37:32 2010, Hao Huan, Input Bandwidth of the DRS Chip 
    Reply  Thu Mar 18 21:38:10 2010, Hao Huan, Serial Interface Frequency of the DRS Chip 
Entry  Sun Mar 21 02:03:44 2010, Hao Huan, PLL Loop Filter Configuration 
Entry  Tue Mar 30 22:57:34 2010, Hao Huan, ROFS Configuration 
Entry  Fri Apr 9 17:14:45 2010, Hao Huan, Baseline Variation In Data 
Entry  Thu May 13 19:14:27 2010, Hao Huan, DVDD Problem of DRS 4 
    Reply  Tue May 18 01:47:59 2010, Hao Huan, DVDD Problem of DRS 4 
    Reply  Wed May 19 02:24:12 2010, Hao Huan, DVDD Problem of DRS 4 
Entry  Wed May 26 19:18:09 2010, Hao Huan, High Frequency Input for DRS 
Entry  Sun Oct 23 23:32:28 2011, Hao Huan, Phase Shift for ADC Readout 
Entry  Wed Dec 14 00:44:37 2011, Hao Huan, Synchronization Delay in the Firmware for 8051 Controller 
Entry  Sat Feb 2 00:13:12 2019, Hans Steiger, Saving Rate (only 15Acq/s) 
Entry  Mon Feb 4 16:42:08 2019, Hans Steiger, Different Distances between the sampling points 
    Reply  Mon Feb 4 17:36:49 2019, Hans Steiger, Different Distances between the sampling points 
Entry  Sat Aug 29 22:00:30 2020, Hans Steiger, Dynamic Range Evaluation Board and Software 
Entry  Mon Aug 31 16:44:12 2020, Hans Steiger, Channel Cascading 
Entry  Mon Sep 15 16:24:41 2014, Hannes Wachter, Timing Calibration Fail 
    Reply  Wed Sep 7 17:28:25 2011, Hannes Friederich, DRS4 and AD9222 
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