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ID Date Author Subjectup Text Attachments
  344   Tue May 13 22:03:47 2014 Luka Pavelicdrsosc binary to cern ROOT file conversionThank you for your fast and very helpful
replay.
  
  345   Tue May 13 23:08:50 2014 Stefan Rittdrsosc binary to cern ROOT file conversion

    

       
            		   
  357   Fri Jun 27 11:23:19 2014 ChengMing Dudrsosc binary to cern ROOT file conversion

    

       
            		   
  362   Wed Jul 30 17:05:38 2014 Stefan Rittdrsosc binary to cern ROOT file conversion

    

       
            		   
  241   Mon Apr 22 15:33:28 2013 Benjamin LeGeyteffect of jitter/alignment between SRCLK and ADC clockHello!
let me apologize in advance if this
has already been covered somewhere and I		   
  242   Mon Apr 22 15:52:53 2013 Stefan Ritteffect of jitter/alignment between SRCLK and ADC clock

    

       
            		  adc_phase.jpg 
  63   Tue Apr 13 10:45:18 2010 lorenzo nerievaluation board used like a counterHi all

  
  64   Tue Apr 13 13:12:43 2010 Stefan Rittevaluation board used like a counter

    

       
            		   
  299   Wed Nov 6 11:53:28 2013 Dmitry Hitsflickering screen for drsoscHi,
 
I have install drs software on ASUS		   
  300   Wed Nov 6 12:25:31 2013 Stefan Rittflickering screen for drsosc

    

       
            		   
  304   Mon Nov 18 11:20:15 2013 Dmitry Hitsflickering screen for drsosc

    

       
            		   
  832   Mon Sep 6 14:42:23 2021 Jiaolonghow to acquire the stop channel with 2x4096 cascading Hi Steffan,

    I have a question
about how to acquire the stop channel: 		   
  834   Sat Sep 18 15:47:50 2021 Stefan Ritthow to acquire the stop channel with 2x4096 cascading The problem must be on your side, since
the Write Shift Register readout works in
other applications with the DRS4 chip. So		   
  Draft   Fri Nov 5 01:10:25 2021 Jiaolonghow to acquire the stop channel with 2x4096 cascading  




   
  850   Fri Nov 5 01:12:10 2021 Jiaolonghow to acquire the stop channel with 2x4096 cascading Thanks for your advice. The problem has
been solved by setting the srin again while reading
out from srout.		   
  774   Mon Oct 14 09:32:33 2019 Danyanghow to acquire the stop position with channel cascadingHi Steffan,

       In DSR4
DATASHEET Rev.0.9 Page13,  there is		  Capture.PNG 
  775   Mon Oct 14 10:14:46 2019 Stefan Ritthow to acquire the stop position with channel cascadingYou first set A3-A0, on the next clock
cycle you issue pulses on srclk, and about
10ns after each clock pulse the output shows		   
  776   Mon Oct 14 11:45:06 2019 Danyanghow to acquire the stop position with channel cascadingI tried the
logic in my designed board.  The results
are shown in the picture: Srout keeps low		  Capture.PNG 
  777   Mon Oct 14 12:56:13 2019 Stefan Ritthow to acquire the stop position with channel cascadingNote that you have to read out the Write
Shift Register only if you do channel cascading,
e.g. configuring the chip with 4x2048 bins		   
  778   Mon Oct 14 13:44:26 2019 Danyanghow to acquire the stop position with channel cascadingYes, firstly I configured the chip
with 4x2048 bins by setting the Write Shift
Register to 01010101b， A3-A0		   
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