 Tue Oct 6 11:20:39 2009, Stefan Ritt, VDD instability 
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It has turned out that the stability of the AVDD and DVDD power supplies for the DRS4 are very critical. On the evaluation board I use a REG1117-2.5,
on our VME board I use a ADP3338-2.5 for the DVDD power supply. When the domino wave is started, the power consumption of the DRS4 chip jumps up by ~40
mA, which has to be compensated by the linear regulator. Following screen shot shows what happens: |
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Wed Oct 7 17:58:20 2009, Stefan Ritt, VDD switch off speed
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It turned out that the VDD switch off speed plays some important role. On our VME board, we have a linear regulator, then a 4.7 uF capacitor, then the
DRS4 chip (DVDD and AVDD). When switching off the VME power, it takes quite some time to discharge the 4.7 uF capacitor, since the DRS4 chip goes into
a high impedance mode if VDD < ~1V. This gives following VDD trace: |
 Fri Oct 16 10:16:10 2009, Stefan Ritt, DSR4 Full Readout Mode
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Jinhong Wang wrote:
Hello Mr. Stefan Ritt |
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Mon Oct 19 09:13:00 2009, Stefan Ritt, BIAS Pin of DRS4
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Jinhong Wang wrote:
Dear Mr. Stefan Ritt. |
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Mon Oct 19 12:46:12 2009, Stefan Ritt, output common mode voltage of DRS4
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Jinhong Wang wrote:
Does it mean that this buffer shifts a voltage of about 1.3V for the primary differential range?
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Wed Nov 4 14:42:22 2009, Stefan Ritt, outline dimension of DRS4
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Jinhong Wang wrote:
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Tue Dec 15 14:38:09 2009, Stefan Ritt, Trigger of DRS4
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Jinhong Wang wrote:
Dear Mr. S. Ritt |
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Mon Dec 21 16:52:08 2009, Stefan Ritt, Trigger of DRS4
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Jinhong Wang wrote:
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Tue Dec 22 09:07:27 2009, Stefan Ritt, Trigger of DRS4
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Jinhong Wang wrote:
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Mon Jan 11 16:32:21 2010, Stefan Ritt, normal_mode_in_drs_exam.cpp
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aliyilmaz wrote:
Dear Mr. S. Ritt |
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Mon Feb 1 08:30:42 2010, Stefan Ritt, Failure In Flashing Xilinx PROM
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Hao Huan wrote:
Hi Stefan, |
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Wed Feb 10 15:35:09 2010, Stefan Ritt, Hello
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pepe sanchez lopez wrote:
hello i am an student and i want to do my final project with drs4 board and i really can´t find |
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Tue Feb 16 09:38:59 2010, Stefan Ritt, Problem reading oscilloscope binary waveform output
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Ron Grazioso wrote:
It looks like the pulse is there but there is something corrupting the data only in binary form. |
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Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
Hi Stefan, |
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Sun Feb 21 13:41:35 2010, Stefan Ritt, Real Time Conference 2010
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Hello,
may I draw your attention to the upcoming Real Time Conference 2010, taking place in Lisbon, Portugal, May 23rd to May 28th, 2010.
http://rt2010.ipfn.ist.utl.pt/ |
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Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
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Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
By the way I have another question: when the default operation mode of the DRS4 chip is used, i.e. WSRIN |
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Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
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Wed Mar 3 17:49:30 2010, Stefan Ritt, Initialization of the Domino Circuit
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Hao Huan wrote:
Hi Stefan, |
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Wed Mar 10 10:07:28 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip
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Hao Huan wrote:
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation |