DRS4 Forum

DRS4 Discussion Forum, Page 9 of 15  Not logged in

Find |  Login |  Help

New entries since: Thu Jan 1 01:00:00 1970

Full | Summary | Threaded | Collapse | Expand     294 Entries

Goto page Previous  1, 2, 3 ... 8, 9, 10 ... 13, 14, 15   Next  All

+    Mon May 2 14:31:28 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each    Wed May 11 15:48:57 2016, SANDJONG Saturnin Orly, Probléme de Calibration de la DRS4     +    Thu May 12 08:16:41 2016, Stefan Ritt, Problem For Software Download     +    Thu May 12 12:38:17 2016, Stefan Ritt, DRS4 Macro to save events     +    Wed Jun 1 23:16:01 2016, Stefan Ritt, problems when stop cell >= 767 ??    Sun Jun 12 08:49:54 2016, Michael, problems of DRS4     +    Wed Jun 15 14:49:00 2016, Stefan Ritt, problems of DRS4    Wed Jun 29 09:10:01 2016, Stefan Ritt, Negative input signals     +    Mon Aug 29 12:51:48 2016, Stefan Ritt, increment write config register on the fly?     +    Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting     +    Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform    Thu Oct 6 15:23:18 2016, Will Flanagan,      +    Tue Oct 11 09:20:04 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s    Tue Oct 11 22:11:26 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s     +    Fri Oct 28 15:51:59 2016, Stefan Ritt, Problems with DRS command line     +    Thu Nov 10 20:54:45 2016, Christian Farina, Missing Header     +    Thu Nov 10 22:07:40 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro     +    Fri Nov 18 16:38:42 2016, Gerard Montarou, LabView     +    Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime()     +    Mon Nov 28 16:52:38 2016, Stefan Ritt, PLL did not lock

Goto page Previous  1, 2, 3 ... 8, 9, 10 ... 13, 14, 15   Next  All

ELOG V3.1.5-fe60aaf