 Fri Oct 30 03:31:54 2009, Jinhong Wang, outline dimension of DRS4 
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Mon Dec 14 10:14:16 2009, Jinhong Wang, Trigger of DRS4
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Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation
of trigger signal to stop DRS4 sampling process for readout of sampled waveform. |
 Mon Dec 21 10:17:05 2009, Jinhong Wang, Trigger of DRS4
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Stefan Ritt wrote:
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Tue Dec 22 01:30:55 2009, Jinhong Wang, Trigger of DRS4
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Stefan Ritt wrote:
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Wed May 12 11:47:39 2010, Jinhong Wang, DRS4 chip model
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Stefan Ritt wrote:
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Fri Jun 18 11:31:20 2010, Jinhong Wang, DVDD Problem of DRS 4
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Stefan Ritt wrote:
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Sat Jun 19 10:09:18 2010, Jinhong Wang, DVDD Problem of DRS 4
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Stefan Ritt wrote:
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Tue Jun 22 10:50:19 2010, Jinhong Wang, Reset of DRS4
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Hi Stefan,
I found DRS draw a lot of current when applied Reset after power on, and the PLL does not work properly. I believe
there was something that I misunderstood. So, what will happen when Reset is applied more than once after power on? . Though the chip worked well |
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Tue Jun 22 11:29:26 2010, Jinhong Wang, Reset of DRS4
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Stefan Ritt wrote:
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Tue Jun 22 11:37:42 2010, Jinhong Wang, Reset of DRS4
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Stefan Ritt wrote:
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Mon Jul 19 12:07:04 2010, Jinhong Wang, Fixed Patter Timing Jitter
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| Hi Stefan, can you give some suggestions on determination of fixed pattern timing jitter of DRS4? Thanks~ |
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Wed Jul 21 10:46:32 2010, Jinhong Wang, ENOB of DRS
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Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip DRS4" , you define DRS4 ENOB as 1Vpp/0.35mv(RMS)
= 11.5bit, where, 1Vpp is the linearity input range, and 0.35mv is the rms voltage after offset correction. What I understand is that 0.35mV is obtained
from DC offset Correction, hence 11.5 bit is for DC input, am i right? If true, what about ENOB for AC input in the whole analog bandwidth? thanks~ |
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Tue Oct 12 03:53:37 2010, Jinhong Wang, Reference design for DRS4 active input buffer
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Stefan Ritt wrote:
The design of high frequency differential input stages with the DRS4 is a challenge, since the chip |
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Mon Jul 4 05:06:00 2011, Jinhong Wang, Fixed Patter Timing Jitter
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Stefan Ritt wrote:
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Tue Jul 12 09:49:08 2011, Jinhong Wang, Fixed Patter Timing Jitter
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Stefan Ritt wrote:
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Thu Dec 27 00:12:12 2012, Jinhong Wang, variation of sampling capacitors
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Hi Stefan,
A quick question, what is the typical variation of the sampling capacitors in DRS4? Will this variation be significant to affect your sampling
result? |
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Thu Dec 27 18:15:14 2012, Jinhong Wang, variation of sampling capacitors
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Stefan Ritt wrote:
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Fri Feb 1 17:43:48 2013, Jinhong Wang, variation of sampling capacitors
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Jinhong Wang wrote:
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Wed Oct 23 17:56:26 2019, John Jendzurski, Computing corrected time from binary data...what is t_0,0?
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In the equations for computing the corrected time for channels other than channel 1, does anyone know what the term t0,0 refers
to? This is the last term in the last equation on page 24 of DRS4 Evaluation Board User’s Manual, Board Revision 5 as of January 2014, Last
revised: April 27, 2016. |
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Wed Oct 25 19:44:25 2023, John Westmoreland, WaveDREAM Design
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Hello All,
Are there any design resources available for the WaveDREAM PCBA's?
Thanks In Advance, |