 Thu May 12 08:16:41 2016, Stefan Ritt, Problem For Software Download
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Can you tell me (screendump) what is the problem on the web site https://www.psi.ch/drs/software-download ?
It should redirect you to
https://www.dropbox.com/sh/qul1cgtm4x7zx13/AADKQ-qGQGdAHPu6OR3vTNY0a?dl=0 |
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Thu May 12 12:38:17 2016, Stefan Ritt, DRS4 Macro to save events
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Dear Maksat,
If your car does not run, and you call the car dealer and tell him "my car does not run", what will the car dealer ask you? Eh... ?
Right ! He will ask "what are the symptoms, what did you try, what did and what did not work". Here it's the same. "was not able to |
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Wed Jun 1 23:16:01 2016, Stefan Ritt, problems when stop cell >= 767 ??
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I cannot confirm the story with the "stop capacitor > 767". It can be seen from your plots that the distribution of stop cells are even,
no holes or bins with double height.
There is an issue with cell 767, but this is when one tries to do simultaneous reading/writing to the chip. This does not really work as writen |
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Wed Jun 15 14:49:00 2016, Stefan Ritt, problems of DRS4
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1. Simultaneous writing and reading is not possible with the DRS4 chip. The manual says differently on p. 14, but due to a bug in the chip waveforms
get clipped at the end if one does that. We hopt to fix this problem in a future version of the chip.
2. You can cascade 2,4 or 8 channels. If you cascade 8 channels and run at 1 GSPS, you digitize a window of 8 us. If you have 16 signals, you |
 Wed Jun 29 09:10:01 2016, Stefan Ritt, Negative input signals
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Hello everybody,
I get often asked if the DRS4 evaluation board can accomodate negative input pulses going to -1V. This is unfortunately not possible, since the
board is mainly for evaluation of the DRS4 chip and should not be seen as a complete oscilloscope with flexible input stage. So the maximum it can do is |
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Mon Aug 29 10:57:33 2016, Stefan Ritt, increment write config register on the fly?
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The issue with "stopping at cell 767" would also affect this mode of operation. Furthermore, the DRS4 chip has only 10 bit register which
records in which cell the event has occured, and where the readout must be started. If you record 8 separate events, you don't know where to start
the readout. |
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Mon Aug 29 12:51:48 2016, Stefan Ritt, increment write config register on the fly?
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The problem is when you change the write config register from 11111111 to 01111111, or from 00001111 to 00000111, then the last 256 sampels of the previous
channel (in the first case #0, in the scond #4) would be overwritten as soon as dwrite =1 again. So you loose 1/4 ef each channel.
Concerning the readout, indeed you can keep track in the FPGA, but only with a certainty of a few cells. This gives some timing inacccuracy of |
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Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting
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Hi Jacob,
you are missing the timing calibration. Each sampling cell has not the same width. Running at 5 GSPS, cell widths scatter from 150 ps to 250
ps. If you integrate these widhts, you get a time scale which can be off by a few ns between chips, something you see in your plot. Here is a paper which |
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Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform
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In the mentioned read_binary.cpp file you have the line where you read the event header
i = fread(&eh, sizeof(eh), 1, f);
The C structure eh now contains the full timestamp, and you can access it with |
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Sun Oct 9 11:39:18 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Can you post a screenshot of your measurement?
Stefan
Danny |
Mon Oct 10 12:03:27 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
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Ok, I got it. The timing resolution is affected by the signal-to-noise ratio over the rise-time of your signal. You find the full formula herer:
https://arxiv.org/abs/1405.4975
Your sine wave input signal has a slow rise time, and therefore limits the time resolution. I reproduced your measurement with a 20 MHz sine |
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Tue Oct 11 09:20:04 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker at the
very left side of the screen, where the yellow marker is at a different position as the others. Hint: a right-click on that slider sets it to zero. The
little streak could be some kind of external noise. |
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Tue Oct 11 22:11:26 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Thank you very much! I will check it tomorrow!
-d
Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker |
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Thu Oct 27 08:29:26 2016, Stefan Ritt, Problems with DRS command line
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[quote="Alexey Lubinets"]Hello, everybody
I have installed the software for the DRS4 Evaluation Board.
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Fri Oct 28 15:51:59 2016, Stefan Ritt, Problems with DRS command line
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No, I absolutely have no idea. Both DRSOsc and drscl use exaclty the same code to access USB.
Stefan
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Tue Nov 8 10:20:52 2016, Stefan Ritt, Missing Header
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The web page from where you downloaded the software contains a sentence "requires libusb-1.0 package". Please install it. This package brings
the "usb.h" header file.
Stefan |
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Wed Nov 9 19:49:07 2016, Stefan Ritt, Missing Header
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Best is to read this paper: https://arxiv.org/abs/1405.4975
The source code for that is in DRS.cpp in the DRS software distribution in the function DRSBoard::CalibrateTiming()
Stefan |
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Thu Nov 10 09:56:04 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro
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Hi,
fread() returns the number of bytes read and zero (I believe) if there is an end of file. So this break statement is a simple end-of-file test.
There might be other erros such as hard disk failures, but these are extremely rare. |
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Thu Nov 10 22:07:40 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro
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You're right, fread() return the number of objects read, so indeed it should be one if successful.
Abhishek
Rajput wrote:
Hello, |
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Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime()
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Cell 700 is arbitrary. You can choose any cell to align the channels to each other. The only requirement is that it's always the same cell for each
event. Historically, Daniel chose cell #700 more or less arbitrary, but later we found out that this works with any cell. So for the publication we went
with cell #0 (and that's why we have t_ch,0 in the paper), but cell #700 was left in the code because of lazyness. Feel free to replace 700 with any |