 Wed Jun 13 13:23:17 2018, Julian Kemp, Maximum analog input voltage
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Dear all,
I have been wondering what the maximum analog input voltage for the DRS4 V5 evaluation board is. It came with a sticker indicating that it is
"2.5V pk Max". On the other hand, when checking the manual (https://www.psi.ch/drs/DocumentationEN/manual_rev50.pdf), it says maximum allowed |
 Wed Jun 13 16:34:28 2018, Julian Kemp, Maximum analog input voltage
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Thank you! That solves my problem.
Stefan
Ritt wrote:
In principle the numbers in the manual are correct. But they relate |
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Fri Oct 13 03:39:01 2017, Jonathan Wapman, Raspberry Pi Connection Failure
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I am currently attempting to use a raspberry pi to connect to the DRS 4 board. I whenever I try to use the DRS Command Line TOol, Revision 21435 to connect
to the drs board, I get the error
"musb_open: libusb_open() error -3" |
Thu May 8 23:23:19 2025, Jonathan Bradshaw, Clarification of full channel readout 
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Hi all
We're working on a new product using the DRS4 IC, and want to do a full readout from cell 0 (not just Region of Interest). I have a
couple of questions I hope you can help me with: |
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Thu May 8 23:41:03 2025, Jonathan Bradshaw, Handling of Write Shift Register and Write Config Register
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Hi all
We're building a product which will use two different operating modes; firstly a long capcture using channel daisy chaining (2048 samples)
and secondly a segmented capture (2 separate captures of 1024 samples each). |
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Tue May 13 04:10:30 2025, Jonathan Bradshaw, Handling of Write Shift Register and Write Config Register
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Hi Stefan
Just so I'm 100% clear; is there no reliable way to perform 2 segmented captures with a single DRS4 IC?
While not a showstopper, this is a bit disappointing. |
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Thu May 15 00:01:20 2025, Jonathan Bradshaw, Handling of Write Shift Register and Write Config Register
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All right, thank you for the clarification.
Stefan
Ritt wrote:
Yes this is correct. Anyhow, even if it would be working, you would |
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Mon Aug 18 06:52:51 2025, Jonathan Bradshaw, Unexpected behaviour following RSRLOAD
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Hello
I'm working to bring up a new capture board using a DRS4 and I'm having a minor problem and a major problem.
Minor problem: if I send a reset signal into the DRS4, the PLL doesn't work right. If I leave NRSESET pin with a wek pullup (and never |
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Tue Aug 19 02:40:58 2025, Jonathan Bradshaw, Unexpected behaviour following RSRLOAD 6x
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Some images
Notes:
top of the puicture shows the logic channels
Red: SRCLK
Blue: SRIN
Green: SROUT
Orange: normally |
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Tue Aug 19 23:10:30 2025, Jonathan Bradshaw, Unexpected behaviour following RSRLOAD
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Turns out it was a damaged DRS4 IC.
I ported the drs4_eval5_app code onto our board and observed much the same misbehaviour. So I bit the bullet and replaced the DRS4 IC,
and things are going better. |
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Wed Oct 25 19:44:25 2023, John Westmoreland, WaveDREAM Design
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Hello All,
Are there any design resources available for the WaveDREAM PCBA's?
Thanks In Advance, |
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Wed Oct 25 19:52:33 2023, John Westmoreland, WaveDREAM Design
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Stefan,
Oh, didn't realize that.
Thanks! |
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Wed Oct 23 17:56:26 2019, John Jendzurski, Computing corrected time from binary data...what is t_0,0?
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In the equations for computing the corrected time for channels other than channel 1, does anyone know what the term t0,0 refers
to? This is the last term in the last equation on page 24 of DRS4 Evaluation Board User’s Manual, Board Revision 5 as of January 2014, Last
revised: April 27, 2016. |
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Fri Oct 16 09:51:03 2009, Jinhong Wang, DSR4 Full Readout Mode
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Hello Mr. Stefan Ritt
In DSR4 DATASHEET Rev.0.8 Page13, I noticed you metioned the samping should occur after
38 ns after the rising edge of SRCLK when the multiplexer is used. So what is suggested value(delay time between sampling and the rising edge of SRCLK) for |
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Mon Oct 19 09:06:43 2009, Jinhong Wang, BIAS Pin of DRS4
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Dear Mr. Stefan Ritt.
Thank u for your timely response on "DSR4 Full Readout Mode", I received it from Professor
Qi An, who is my PhD supervisor. |
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Mon Oct 19 11:26:29 2009, Jinhong Wang, output common mode voltage of DRS4
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Hello Mr. Stifan.Ritt
In the DSR4 datasheet, it is mentioned
that there is an additional buffer at each analog output, this buffer shifts the the differential range of -0.5V~0.5V to 0.8V~1.8V. Does it mean that this
buffer shifts a voltage of about 1.3V for the primary differential range?
Again for the differential |
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Fri Oct 30 03:31:54 2009, Jinhong Wang, outline dimension of DRS4
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Mon Dec 14 10:14:16 2009, Jinhong Wang, Trigger of DRS4
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Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation
of trigger signal to stop DRS4 sampling process for readout of sampled waveform. |
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Mon Dec 21 10:17:05 2009, Jinhong Wang, Trigger of DRS4
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Stefan Ritt wrote:
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Tue Dec 22 01:30:55 2009, Jinhong Wang, Trigger of DRS4
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Stefan Ritt wrote:
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