Hi!

I'm using the DRSOsc program, and I have a question that I need a bit clarified;

When triggering using AND between two channels, am I then triggering on rising/falling edge of both channels, or on the actual values?

That is, is it the change in value that it triggers on, or when the actual value goes above a certain threshold?

Using AND, it seems like I get a trigger when one (CH2) is above its trigger value (sometimes quite far above), and the other (CH1) changes to go above its trigger value. This works for my purposes, which is nice, but I just want to be sure I understand why it works. Ideally, I'd like to trigger when one of my channels is above a certain value, and the other has a rising edge above a certain value.

I'm sorry if it's a silly question! I've just noticed that the Keysight oscilloscopes I've used can only do one channel with a rising edge at a time when doing a logic trigger, and I thought the same thing might be going on in the background here (which would be ideal for my purposes).

Kind regards,

Håkan Wennlöf

Hi, 

I would like to save the waveform in a .dat binary file using drs_exam.cpp.

I know the distributed software allows us to save as binary files with the save button, but I currently need to save multiple runs using a script.

I've seen that drs_exam.cpp can save the waveform as .txt files.

Is there any .cpp file or function that allows us to save the waveforms in binary format (.dat)?

Thank you for your help. 

Hi,

while trying to create python bindings for the DRS stuff using SWIG 2.0.4, two undefined methods prevent the python interpreter from loading the generated shared library. These methods are:

• int DRSBoard::SetADCActive(unsigned char)
• bool ResponseCalibration::Calibrate(unsigned int,unsigned int,float *,float *,float,bool)

Can we safely removed those methods from the DRS header files or (what I have actually done) is it better to fake some empty implementation in the input file to SWIG?

Another minor issue is that the python interpreter always terminates with a SegFault after script termination. I had not yet time to track that down...

Thanks & regards

Hermann-Josef

Hi,

is there any (obvious) reason why it is not possible (or not indended) to repeat the time calibration of a DRS4 eval board several times. I get the shown error message from the 'drscl' tool as well when I try to call the corresponding method in the support library:

mathes@ikauger5:~/src/DRS4> drs-4.0.1/drscl
DRS command line tool, Revision 20430
Type 'help' for a list of available commands.

Found DRS4 board  0 on USB, serial #2362, firmware revision 17662

B0> tcalib
Enter calibration frequency [GHz]: 5
Creating Timing Calibration of Board #2362
[==================================================]
B0> tcalib 5
Creating Timing Calibration of Board #2362
Error performing timing calibration, please check waveforms

As I will be in holidays, the answer is not urgent.

Thanks

 -- Hermann-Josef

 Hi Stefan,

thanks for the quick reply, I know that this solution works with drscl but not within my code.

I tried to track it down, but gave up very soon. Seems as if AnalyzeWF() which is called by CalibrateTiming() finds to much zero-crossings when it is called the second time.

Regards

  -- Hermann-Josef

Hi,

the latest software drs-5.0.0.tar.gz fails to compile on my freshly installed SuSE 13.1 whereas the previous 4.0.1 is compiling out-of-the-box.

My system has the wxWidgets 2.8.12 which is probably together with gcc 4.8.1 the reason of the problem. I applied a number of corrections, mainly some sort of proper (?) typecasts, a patch file is attached.

Maybe you could consider to take them into account for the next patch release?

Thanks and best regards

Hermann-Josef

Hi,

we want to run two instances of our little DRS DAQ program but obviously the first instance started always claims all DRS boards for itself and the other one exits with an error. The 2 boards used in the example below have the serial number # 2413 and #2414 and are v5 boards.

The first one:

mathes@ikauger5:~/src/DRS4/Cpp> ./drsdaq -b 2413
DRSController: found board with serial number #2413
DRSController: found board with serial number #2414
DRSController: using board with serial number #2413
CalibratedFrequency= 1.00721
====================================
DRS type:            DRS4
Board type:          9
Serial number:       2413
Firmware revision:   21260

...
And the second one:

mathes@ikauger5:~/src/DRS4/Cpp> ./drsdaq -b 2414
musb_open: usb_set_configuration() error -6
musb_open: Found USB device 0x04b4:0x1175 instance 0, but cannot initialize it: please check permissions on "/proc/bus/usb/1/7" and "/dev/bus/usb/1/7"
USB successfully scanned, but no boards found
...

How can our goal be achieved?

Thanks

Hermann-Josef

Hi, Stefan,

I found that my collaborator bought 2 older version of evaluation board before.
They are the version 1.2 in plastics case with firmware 13191.

Can I upgrade the firmware from 13191 to 13279?
I'm wondering if the older version of evaluation board is working with firmware 13279.

Thanks,
Heejong

 Hi, Stefan,

drs_exam.cpp is working good to read-out one board.

Now I would like to read-out two boards at the same time using the same trigger( external or internal).

I'm trying to understand and modify the original code for control two board.

Meantime, it would be very appreciated if you give any tips for this.

Thanks,

Heejong

Hello,

I'm using DRS4 evaluation board version4 in Linux (Scientific Linux 5).

Version4 software (drs-4.0.0) was installed without any troubles.

The oscilloscope interfrace program (drsosc) is working fine with version4 software.

But when I tried drs_exam program, it doesn't work as expected.

(500 mV positive (width 50ns)  pulse is connected to Ch#1).

It keeps waiting trigger in the first event.

In the previous version (board/software drs-3.0.0), drs_exam program worked well.

I'm wondering if anybody is using drs_exam with V4 evaluation board.

Any comments/help would be welcomed.

Thanks,

Heejong

Hello Stefan,

Thanks for your prompt reply.

drs_exam is working now after modification as above.

By some trials, I found that external trigger is possible by 'b->EnableTrigger(1,0); b->SetTriggerSource(1<<4);'

Best,

Heejong

Hi Stefan,

    I have an old-version DRS4 evaluation board which doesn't have the latest firmware. I tried to flash the drs_eval1.ipf boundary scan chain into the XCF02S PROM with Xilinx IMPACT, and the firmware seemed to go through into the PROM. However, when I started the DRS command line interface to test the firmware it kept on reporting errors like

musb_write: requested 10, wrote -116, errno 0 (No error)

musb_read error -116

musb_write: requested 10, wrote -22, error 0 (No error)

musb_read error -116

and so on. Finally the program made a dumb recognition of the board as

Found mezz. board 0 on USB, serial #0, firmware revision 0

Do you have any idea which caused this problem? Thanks!

Hi Stefan,

    in the latest DRS4 datasheet I only saw your data of the DRS4 PLL locking time for 6GSPS sampling speed, with other rows "TBD". Have you tried those lower frequencies? According to the datasheet I think the PLLLCK should be stabily low when the PLL is locked; am I right? However when I try my design with the DRS4 chip and feed the reference clock signal at 0.5MHz or 2MHz, the PLLLCK I get can never stabilize. There could be some problem in the PCB circuit connection, but I want to confirm with you since I'm confused with those "TBD" blanks.

    Thanks a lot!

Thanks! I see. The capacitor is important. However I'm a little confused... If PLLLCK=DTAP XOR REFCLK, shouldn't it integrate to low instead of high when the two clocks are in phase? I must have some misunderstanding here. So if we ignore any realistic complexity and assume DTAP is perfectly locked with REFCLK, will PLLLCK be always low or high? I'm sorry I do not know how the DRS internal PLL and its input/output work...

 Got it. Thank you! By the way I have another question: when the default operation mode of the DRS4 chip is used, i.e. WSRIN is fed internally to WSROUT, at the external pins is it necessary to leave the WSRIN open? Or any input through the pin will not affect the Domino wave running? Also I observe that WSROUT will be always low when the chip is running in this mode; is it the supposed behavior?

 Sorry; WSROUT also has an inverter? Actually I have one more stupid question about the shift registers: when we assert the address bits to operate on one shift register, e.g. WSR, we use SRIN to give input and SROUT to read output; but how does the shift register know whether we're reading or writing? Or it will just receive input from SRIN and give output at SROUT at the same time?

Thank you so much!

Hi Stefan,

    I read in the datasheet that every time after power up the Domino wave in DRS4 needs to be started and stopped once to initialize the Domino circuit. However in your firmware it seems the chip immediately goes into the idle state after reset. Is that Domino circuit initialization really necessary?

    Also an aside question: in your firmware the readout process has the SRCLK sent to DRS4 only about 200ns later after RSRLOAD gets asserted instead of immediately following RSRLOAD. Is there any reason for that?

    Thanks a lot!

Hi Stefan,

    thanks to your help I can now successfully keep the Domino wave running at a stable frequency and maintain the channel cascading information in the Write Shift Register. (Since you told me WSR always reads and writes at the same time, I think I need to rewrite the information back every time after reading out from WSR to decide from which channel my data come, don't I?)

    However I'm still having difficulty in reading out from the DRS cells. I use the ROI readout mode and assume as long as I give a pulse on RSRLOAD the data will come out one by one. However, what I get is just a constant with some noise, which seems I'm always reading from the same cell. Actually I'm not very clear about how it works. What's the mechanism for RSRLOAD  and do I have to initialize the Read Shift Register to use the ROI mode? Also I read in the datasheet that WSROUT will give RSR output when DWRITE is low. Sometimes I see some random bits from this output and sometimes I see all zero's. What is the reasonable output I should see from WSROUT, say, when I'm running in the transparent mode with DWRITE low?

    Thank you very much!

Hi Stefan,

    I tried again and confirmed the problem... In the full readout mode I could successfully read out all the data, but in the ROI mode if I naively apply a pulse at RSRLOAD the results are not right. Is there anything I should be careful about in the ROI readout mode?

    Thanks!

Hi Stefan,

    in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation board firmware SRCLK is toggled at rising edges of the internal 33MHz clock, i.e. the frequency of SRCLK itself is 16.5MHz instead. Is that frequency better than 33MHz?

    Thanks!