 Wed Aug 7 15:05:59 2013, Hermann-Josef Mathes, Repeated time calibration
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Hi,
is there any (obvious) reason why it is not possible (or not indended) to repeat the time calibration of a DRS4 eval board several times. I get |
 Wed Aug 7 15:20:33 2013, Hermann-Josef Mathes, Repeated time calibration
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Stefan Ritt wrote:
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Wed Mar 5 21:54:13 2014, Hermann-Josef Mathes, Software drs-5.0.0 fails to compile (drsosc) 
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Hi,
the latest software drs-5.0.0.tar.gz fails to compile on my freshly installed SuSE 13.1 whereas the previous 4.0.1 is compiling out-of-the-box.
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Mon Mar 16 16:07:39 2015, Hermann-Josef Mathes, Running 2 instances of a DRS DAQ program
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Hi,
we want to run two instances of our little DRS DAQ program but obviously the first instance started always claims all DRS boards for itself and
the other one exits with an error. The 2 boards used in the example below have the serial number # 2413 and #2414 and are v5 boards. |
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Mon Apr 5 17:50:39 2010, Heejong Kim, version 1.2 evaluation board with firmware 13279?
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Hi, Stefan,
I found that my collaborator bought 2 older version of evaluation board before.
They are the version 1.2 in plastics case with firmware
13191.
Can I upgrade the firmware from 13191 to 13279?
I'm wondering if the older version of evaluation board is working with firmware 13279.
Thanks,
Heejong
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Mon Apr 5 17:57:41 2010, Heejong Kim, Simple example application to read a DRS evaluation board
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Stefan Ritt wrote:
Several people asked for s simple application to guide them in writing their own application to read out |
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Thu Jan 19 23:26:26 2012, Heejong Kim, drs_exam.cpp for evaluation board version 4
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Hello,
I'm using DRS4 evaluation board version4 in Linux (Scientific Linux 5).
Version4 software (drs-4.0.0) was installed without any troubles. |
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Fri Jan 20 23:50:39 2012, Heejong Kim, drs_exam.cpp for evaluation board version 4
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Stefan Ritt wrote:
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Sun Jan 31 23:52:15 2010, Hao Huan, Failure In Flashing Xilinx PROM
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Hi Stefan,
I have an old-version DRS4 evaluation board which doesn't have the latest firmware. I tried to flash the drs_eval1.ipf boundary
scan chain into the XCF02S PROM with Xilinx IMPACT, and the firmware seemed to go through into the PROM. However, when I started the DRS command line interface |
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Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4
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Hi Stefan,
in the latest DRS4 datasheet I only saw your data of the DRS4 PLL locking time for 6GSPS sampling speed, with other rows "TBD".
Have you tried those lower frequencies? According to the datasheet I think the PLLLCK should be stabily low when the PLL is locked; am I right? However |
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Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Wed Mar 3 17:36:31 2010, Hao Huan, Initialization of the Domino Circuit
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Hi Stefan,
I read in the datasheet that every time after power up the Domino wave in DRS4 needs to be started and stopped once to initialize
the Domino circuit. However in your firmware it seems the chip immediately goes into the idle state after reset. Is that Domino circuit initialization |
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Thu Mar 4 19:14:10 2010, Hao Huan, Readout of DRS Data
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Hi Stefan,
thanks to your help I can now successfully keep the Domino wave running at a stable frequency and maintain the channel cascading
information in the Write Shift Register. (Since you told me WSR always reads and writes at the same time, I think I need to rewrite the information back |
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Fri Mar 5 23:29:04 2010, Hao Huan, Readout of DRS Data
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Hao Huan wrote:
Hi Stefan, |
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Tue Mar 9 23:28:45 2010, Hao Huan, Serial Interface Frequency of the DRS Chip
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Hi Stefan,
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation board firmware SRCLK is
toggled at rising edges of the internal 33MHz clock, i.e. the frequency of SRCLK itself is 16.5MHz instead. Is that frequency better than 33MHz? |
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Thu Mar 11 21:37:32 2010, Hao Huan, Input Bandwidth of the DRS Chip
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Hi Stefan,
I read in the DRS datasheet that the input bandwidth if 950MHz. However, it also says the output bandwidth in the transparent
mode is 50MHz. Since in the transparent mode the input is routed to the output, does it mean the input bandwidth also gets reduced in the transparent mode? |
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Thu Mar 18 21:38:10 2010, Hao Huan, Serial Interface Frequency of the DRS Chip
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Stefan Ritt wrote:
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Sun Mar 21 02:03:44 2010, Hao Huan, PLL Loop Filter Configuration
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Hi Stefan,
in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF. If I want to run the Domino
wave nominally at 1GHz, i.e. with a reference clock frequency around 0.5MHz, is there any recommended loop filter configuration? Is the setup of the evaluation |