 Tue Mar 30 22:57:34 2010, Hao Huan, ROFS Configuration
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Hi Stefan,
according to the DRS4 datasheet, if we want an input range centered around U0, the ROFS should be 1.55V-U0. However when I read
the codes of the evaluation board application, ROFS seems to be 1.6V-1.25*U0 where the coefficient 1.25 is said to come from sampling cell charge injection |
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Fri Apr 9 17:14:45 2010, Hao Huan, Baseline Variation In Data
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Hi Stefan,
when I sample a constant input with the DRS 4 chip, there was a baseline variation showing up as a saw-tooth pattern which grows
with the absolute value of the differential input. Do you think this is the kind of baseline variation mentioned in the evaluation board manual, i.e. coming |
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Thu May 13 19:14:27 2010, Hao Huan, DVDD Problem of DRS 4
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Hi Stefan,
on our board some DRS chips draw a lot of current through DVDD after power-up and heat up significantly--it is true that our
board doesn't have weak pull-down resistors at DENABLE and DWRITE output pins of FPGA, so this problem might have been caused by that, but a reinitialization |
 Tue May 18 01:47:59 2010, Hao Huan, DVDD Problem of DRS 4
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Stefan Ritt wrote:
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Wed May 19 02:24:12 2010, Hao Huan, DVDD Problem of DRS 4
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Stefan Ritt wrote:
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Wed May 26 19:18:09 2010, Hao Huan, High Frequency Input for DRS
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Hi Stefan,
I read in the DRS datasheet that the bandwidth for the transparent mode OUT+ is only 200MHz which I think cannot be improved
by any active input buffer; so if you want to operate the chip for really high frequency input, would it be better to feed on-board discriminators not |
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Sun Oct 23 23:32:28 2011, Hao Huan, Phase Shift for ADC Readout
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Dear Dr. Ritt,
In the DRS 4 datasheet it is recommended to sample the analog output of the chip after 8~10 ns of the SRCLK edge for it to stablize
and thus a phase shift between SRCLK and the ADC sampling clock is necessary. However in the latest version of the evaluation board firmware the phase-shifted |
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Wed Dec 14 00:44:37 2011, Hao Huan, Synchronization Delay in the Firmware for 8051 Controller
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Hi Stefan,
I have a question regarding the DRS 4 evaluation board firmware for the 8051 controller embedded in the CY7C68013 USB chip:
on the board the controller is running at 12 MHz and the FIFO interface of the USB chip is running at 30 MHz, so the number of delay cycles for synchronization |
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Sat Feb 2 00:13:12 2019, Hans Steiger, Saving Rate (only 15Acq/s)
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Dear All,
when I use my Evaluation Board with some PMTs I can digitize 450 Acq/s or so. But when I want to save the waveforms the rate goes down. The Acqu. |
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Mon Feb 4 16:42:08 2019, Hans Steiger, Different Distances between the sampling points
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Dear All,
with the older software for my V5 Board i did not have the problem, that the distance between the sampling points (in time) is not the same (e.g.
a sampling point all 200ps for 5GS/s). |
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Mon Feb 4 17:36:49 2019, Hans Steiger, Different Distances between the sampling points
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Sorry.... but is there a solution or a Root Macro, that reads the waveforms into a Root-Tree? I simply can not work anymore with the data.
Can you tell me, which software was in use in early 2017?
All the best, |
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Sat Aug 29 22:00:30 2020, Hans Steiger, Dynamic Range Evaluation Board and Software
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Dear Evaluation Board Team,
currently I am facing the problem of digitizing pulses with an amplitude of -0.6V to -0.8V. As the dynamic range of the board is 1Vpp, this should |
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Mon Aug 31 16:44:12 2020, Hans Steiger, Channel Cascading
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Dear All,
I have a board with Channel Cascading Option. I have the problem, that it seems to be impossible to run all 4 Channels simultaneously for digitizing
pulses. I can just run even or odd channels but not even and odd ones? If I run in combined option, My question: If a board comes with this combined option, |
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Mon Sep 15 16:24:41 2014, Hannes Wachter, Timing Calibration Fail
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Hi,
has anyone experienced a shutdown of the DRSosc.exe or DRScl.exe when executing a Timing Calibration? Also, when we add the command b->CalibrateTiming(NULL);
to the drs_exam.cpp and run the exe, our program shuts down immediately and windows shows an error message (identical to DRSosc and DRScl). |
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Wed Sep 7 17:28:25 2011, Hannes Friederich, DRS4 and AD9222
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Guillaume Blanchard wrote:
Normal
0
21
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Wed Nov 21 08:34:52 2012, Gyuhee Kim, Question for using Multi board
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Hi.
I have 2 DRS4 evaluation V4 boards, and I want to use these 2 board to multi board DAQ system for 4 ch vs 4 ch DAQ. |
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Wed Nov 21 08:48:00 2012, Gyuhee Kim, Question for using Multi board
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Stefan Ritt wrote:
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Mon Dec 3 08:32:28 2012, Gyuhee Kim, Another question about using multi boards.
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Hi.
I asked about using multi boards some days ago, and I got answer to use external trigger. (Thanks Stefan!) |
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Mon Dec 3 11:40:35 2012, Gyuhee Kim, Another question about using multi boards.
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Stefan Ritt wrote:
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Wed Sep 7 16:45:17 2011, Guillaume Blanchard, DRS4 and AD9222
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Normal
0
21
false
false
false
MicrosoftInternetExplorer4
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