 Wed Jan 15 17:37:21 2014, Stefan Ritt, DRS4 installation on Windows 8 issues
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Andrey Kuznetsov wrote:
I'm also having trouble installing drivers and running DRSOsc program |
 Tue May 19 14:14:45 2015, Ilja Bekman, DRS4 firmware UCF constraints
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Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.
I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that
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Fri May 22 14:25:45 2015, Stefan Ritt, DRS4 firmware UCF constraints 
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> Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.
>
> I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that
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Tue May 26 11:27:27 2015, Felix Bachmair, DRS4 firmware UCF constraints
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> > Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.
> >
> > I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that
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Fri Jun 5 12:07:38 2015, Stefan Ritt, DRS4 firmware UCF constraints
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I presume you have several evaluation boards and want to run them in sync, right?
This can be either made in daisy-chain mode (see manual page 25). In this case only the master board can trigger the slave boards. If you need to trigger |
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Fri Jun 5 13:15:35 2015, Felix Bachmair, DRS4 firmware UCF constraints
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Hi Stefan,
No we only use one evaluation board. We use the evaluation board as a part of our beam test setup. It includes a telescope based on the current PSI46V2.1
CMS Pixel chip and a trigger logic board for triggering the telescope and the evaluation board. This includes a
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Fri Jun 5 13:29:55 2015, Stefan Ritt, DRS4 firmware UCF constraints
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Do the following:
Use the TRG OUT of the evaluation board as a "busy". Only if this signal goes low (meaning that the readout of the board is complete and the board has |
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Fri Jun 5 13:32:03 2015, Stefan Ritt, DRS4 firmware UCF constraints
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Actually we should take this offline not to pester other DRS users which are not interested in this topic. Please call me directly (3728) at PSI.
/Stefan |
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Thu Nov 1 20:08:33 2012, hongwei yang, DRS4 firmware
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Hi,
We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I
look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto |
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Thu Nov 1 20:17:42 2012, Stefan Ritt, DRS4 firmware
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hongwei yang wrote:
Hi, |
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Thu Nov 1 20:21:44 2012, hongwei yang, DRS4 firmware
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Stefan Ritt wrote:
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Thu Nov 1 20:25:53 2012, hongwei yang, DRS4 firmware
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hongwei yang wrote:
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Thu Nov 1 20:32:03 2012, Stefan Ritt, DRS4 firmware
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hongwei yang wrote:
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Thu Nov 1 20:46:53 2012, hongwei yang, DRS4 firmware
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Stefan Ritt wrote:
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Sat Oct 15 04:45:25 2011, Aurelien Bouvier, DRS4 eval board: readout rate
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Hi,
Our setup uses a DRS4 evaluation board (version 2.0).
Although we trigger the board at a rate of ~4kHz (on channel2), readout through USB2 is only happening at a rate of ~125Hz. |
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Sat Oct 22 00:40:02 2011, Stefan Ritt, DRS4 eval board: readout rate
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Aurelien Bouvier wrote:
Hi, |
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Wed Apr 5 12:40:16 2017, Martin Petriska, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
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I would like to implement fpga firmware changes for DRS4 eval board v4 to put there posibility for standard coincidence (for example to get triger
on two short (5ns pulses from Plastic scintilator) in 100ns coincidence window), Similar but more complex was done for eval v.5 boards ( https://forge.physik.rwth-aachen.de/projects/drs4-rwth
) Im beginner in state of FPGA design, but hope it will be not so dificult to implement same functionality in eval4 board. Is there any SVN server |
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Mon Apr 10 10:48:03 2017, Stefan Ritt, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
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You have to download the package for your board, which then includes also the correct firmware for your board. If you have a V4 board, your firmware
is in drs-4.0.2.tar.gz which you can download from Dropbox at https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
Martin |
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Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study
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We have been using DRS4 IC in our design for quite some time and it is giving good performance.
Till now we were using Domino wave frequency as 1 GSPS by use of reference clock to DRS4 and internal PLL of DRS4. Recently we tried to use 4GSPS
by modifying the reference clock. |
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Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study
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The Domino wave is most stable at 5 GSPS, slowly degrades down to 3-2 GSPS, and at 1GSPS gets some significant jitter. This is for internal reasons in
the chip and cannot be compensated by the loop filter. It is therefore important to run it as fast as possible if you want to achieve best timing resolution.
As a rule of thumb, the jitter at 5 GSPS is about 20-25 ps, and at 1 GSPS it is maybe 150 ps. If you require good timing resolution, you can use the 9th |