 Thu Nov 1 20:21:44 2012, hongwei yang, DRS4 firmware
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Stefan Ritt wrote:
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Thu Nov 1 20:25:53 2012, hongwei yang, DRS4 firmware
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hongwei yang wrote:
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Thu Nov 1 20:32:03 2012, Stefan Ritt, DRS4 firmware 
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hongwei yang wrote:
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Thu Nov 1 20:46:53 2012, hongwei yang, DRS4 firmware
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Stefan Ritt wrote:
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 Sat Oct 15 04:45:25 2011, Aurelien Bouvier, DRS4 eval board: readout rate
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Hi,
Our setup uses a DRS4 evaluation board (version 2.0).
Although we trigger the board at a rate of ~4kHz (on channel2), readout through USB2 is only happening at a rate of ~125Hz. |
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Sat Oct 22 00:40:02 2011, Stefan Ritt, DRS4 eval board: readout rate
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Aurelien Bouvier wrote:
Hi, |
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Wed Apr 5 12:40:16 2017, Martin Petriska, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
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I would like to implement fpga firmware changes for DRS4 eval board v4 to put there posibility for standard coincidence (for example to get triger
on two short (5ns pulses from Plastic scintilator) in 100ns coincidence window), Similar but more complex was done for eval v.5 boards ( https://forge.physik.rwth-aachen.de/projects/drs4-rwth
) Im beginner in state of FPGA design, but hope it will be not so dificult to implement same functionality in eval4 board. Is there any SVN server |
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Mon Apr 10 10:48:03 2017, Stefan Ritt, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
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You have to download the package for your board, which then includes also the correct firmware for your board. If you have a V4 board, your firmware
is in drs-4.0.2.tar.gz which you can download from Dropbox at https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
Martin |
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Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study
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We have been using DRS4 IC in our design for quite some time and it is giving good performance.
Till now we were using Domino wave frequency as 1 GSPS by use of reference clock to DRS4 and internal PLL of DRS4. Recently we tried to use 4GSPS
by modifying the reference clock. |
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Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study
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The Domino wave is most stable at 5 GSPS, slowly degrades down to 3-2 GSPS, and at 1GSPS gets some significant jitter. This is for internal reasons in
the chip and cannot be compensated by the loop filter. It is therefore important to run it as fast as possible if you want to achieve best timing resolution.
As a rule of thumb, the jitter at 5 GSPS is about 20-25 ps, and at 1 GSPS it is maybe 150 ps. If you require good timing resolution, you can use the 9th |
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Sun May 2 18:36:14 2010, Ignacio Diéguez Estremera, DRS4 chip model
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Hi all,
i'm an electronics engineering student at UCM (Madrid) working on my master's thesis within the CTA collaboration. I'm designing the readout electronics
for the telescope's camera, and i'm focusing in using GAPDs instead of PMTs and using the domino chip for the sampling of the signal. I was wondering if |
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Mon May 3 11:09:12 2010, Stefan Ritt, DRS4 chip model
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Ignacio Diéguez Estremera wrote:
Hi all, |
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Mon May 3 17:06:02 2010, Ignacio Diéguez Estremera, DRS4 chip model
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Stefan Ritt wrote:
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Mon May 3 17:10:29 2010, Stefan Ritt, DRS4 chip model
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Ignacio Diéguez Estremera wrote:
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Mon May 3 23:21:55 2010, Ignacio Diéguez Estremera, DRS4 chip model
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Stefan Ritt wrote:
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Tue May 4 11:26:21 2010, Stefan Ritt, DRS4 chip model
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Ignacio Diéguez Estremera wrote:
So i guess i won't be able to include drs4 in my simulations :-(. Any other |
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Tue May 4 16:23:16 2010, Ignacio Diéguez Estremera, DRS4 chip model
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Stefan Ritt wrote:
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Wed May 12 11:47:39 2010, Jinhong Wang, DRS4 chip model
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Stefan Ritt wrote:
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Wed May 12 16:26:12 2010, Stefan Ritt, DRS4 chip model
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Jinhong Wang wrote:
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Wed Sep 7 16:45:17 2011, Guillaume Blanchard, DRS4 and AD9222
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