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  116   Fri Feb 25 10:13:51 2011 Stefan RittAnnouncement digital pulse processing workshop

Dear colleague,

if you live not so far from Zurich, you might be interested in this workshop:

http://www.xtronix.ch/hep/psi_workshop.htm

This is a combined PSI-CAEN presentation of digitizer hardware including the new V1742 board based on the DRS4 chip. The workshop will also show how digital pulse processing can be used to effectively extract time and energy from detector signals, and thus replace more and more traditional analog electronics. Please register at the above site if you are interested.

Best regards,

    Stefan Ritt

  6   Mon Apr 27 15:09:49 2009 Stefan RittAmplitude and Timing calibration for DRS4 Evaluation Board

This is a quick notification to all users of the current DRS4 evaluation board.

As you all know, the DRS4 chip needs some calibration for each individual cell which corrects the offset and the non-equidistant width in time. While the first evaluation boards have been shipped without this calibration, the current version of the software implements a full amplitude and timing calibration. The offset correction reduces the noise of the board by almost an order of magnitude to below 1 mV RMS. The timing calibration using an on-board reference clock allows a timing accuracy in the order of 10 ps. To illustrate that the following two pictures show a reference clock signal before and after timing calibration:

uncal.png

cal.png

The integral temporal nonlineairy at 5 GSPS before timing calibration is about 600 ps as can be seen by the jitter of the overlaid waveforms.

In order to do a timing calibration, the firmware revison 13297 or later is required. The current software package 2.1 contains an updated firmware, but unfortunately one needs a Xilinx download cable to flash this new firmware (see http://drs.web.psi.ch/download/ under "Software Versions"). If some people want an update but do not want to buy such a cable, we offer a free update at our institute (just the postage has to be paid). The old evaluation board (Rev. 1.0, plastic housing) can unfortunately not be updated.

After the offset calibration is made, there are small (~20mV) short spikes left. They probably come from some cross-talk between the USB interface and the analog part of the board. This is currently under investigation. If new updates become available, they will be announced in this forum.

 

April 27th, 2009,

Stefan Ritt

  584   Sat Jan 28 14:11:58 2017 Danny PetschkeAND trigger problems

 Dear Stefan,

I have 2 identical pulses as a splittet signal with an amplitude of 300mV. Range is -0.5-0.5V, 5.12GSamp using the Evaluation-Board. Both signals are triggered in AND logic. One of the signals is delayed by a fixed value of 1-50ns for testing. On increasing the trigger Level from 10% to 50% of amplitude (pulse rise time is 2.5ns) pulses cannot anymore triggered above 4-5ns delay. It means there is a proportionality between the trigger level and the available range where 2 signals can be triggered in AND logic (Time-difference between 2 pulses). Do I anything misunderstand or is the time the comparator needs by higher trigger Levels for comparation longer than the 200ns at 5.12GSamp?

Board was timing and voltage calibrated before.

Thx

Danny

  585   Mon Jan 30 16:37:33 2017 Stefan RittAND trigger problems

In the evaluation board we use an ADCMP601 comparator, which has a setup and hold time of 4.6 ns. So a pulse which exceeds the threshold for less than 4.6 ns will not trigger the board. If you AND two signals together, an additional constraint might apply on the coincidence pulse. This is processed in the FPGA, but once it becomes too short, it won't trigger the board as well. I never made a real measurement of that, but I would not be suprised if the coicidence signal (output of AND), needs to be at least 4-5 ns wide.

If you need more refined trigger conditions, make yourself an old-fashioned external trigger (with NIM modules for example), stretch the output to 10 ns and feed it into the external trigger input of the DRS4 board (5V CMOS logic, not NIM!).

Best,

Stefan

Danny Petschke wrote:

 Dear Stefan,

I have 2 identical pulses as a splittet signal with an amplitude of 300mV. Range is -0.5-0.5V, 5.12GSamp using the Evaluation-Board. Both signals are triggered in AND logic. One of the signals is delayed by a fixed value of 1-50ns for testing. On increasing the trigger Level from 10% to 50% of amplitude (pulse rise time is 2.5ns) pulses cannot anymore triggered above 4-5ns delay. It means there is a proportionality between the trigger level and the available range where 2 signals can be triggered in AND logic (Time-difference between 2 pulses). Do I anything misunderstand or is the time the comparator needs by higher trigger Levels for comparation longer than the 200ns at 5.12GSamp?

Board was timing and voltage calibrated before.

Thx

Danny

 

  616   Thu Jun 8 14:26:23 2017 Rebecca SchmitzAND Trigger problems with 2-3 channels

Hello,

I work with the DRS4 Evaluation Board V5 and I have a problem with the software.

I have a problem with the AND trigger setting.
For this I have chosen the AND trigger function. However, when ONE channel senses an impulse, it triggers. I'm not able to see signals in the other channels, which I selected for the coincidence.

What is the cause of this? Maybe the time window?

I would like to measure a coincidence with two or three random channels. Is it possible?

Thanks for the help.

Rebecca

  617   Thu Jun 8 15:52:20 2017 Stefan RittAND Trigger problems with 2-3 channels

Can you post a screenshot where I can see the channel waveforms, the configuration and the trigger settings?

Stefan

Rebecca Schmitz wrote:

Hello,

I work with the DRS4 Evaluation Board V5 and I have a problem with the software.

I have a problem with the AND trigger setting.
For this I have chosen the AND trigger function. However, when ONE channel senses an impulse, it triggers. I'm not able to see signals in the other channels, which I selected for the coincidence.

What is the cause of this? Maybe the time window?

I would like to measure a coincidence with two or three random channels. Is it possible?

Thanks for the help.

Rebecca

 

  618   Fri Jun 9 09:44:33 2017 Rebecca SchmitzAND Trigger problems with 2-3 channels

Hello,

It seems that a coincidence with two fixed channels suddenly works. I don't know why.

Screenshot 1 shows the trigger settings for the coincidence with two channels.
Screenshot 2 shows the oscilloscope surface.
Screenshot 3 shows the configuration. In the background there is a coincidence with three channels.

In contrast to the coincidence with two channels this doesn't look good.

Rebecca

Stefan Ritt wrote:

Can you post a screenshot where I can see the channel waveforms, the configuration and the trigger settings?

Stefan

Rebecca Schmitz wrote:

Hello,

I work with the DRS4 Evaluation Board V5 and I have a problem with the software.

I have a problem with the AND trigger setting.
For this I have chosen the AND trigger function. However, when ONE channel senses an impulse, it triggers. I'm not able to see signals in the other channels, which I selected for the coincidence.

What is the cause of this? Maybe the time window?

I would like to measure a coincidence with two or three random channels. Is it possible?

Thanks for the help.

Rebecca

 

 

Attachment 1: Screenshot1.png
Screenshot1.png
Attachment 2: Screenshot2.png
Screenshot2.png
Attachment 3: Screenshot3.png
Screenshot3.png
  620   Thu Jun 22 21:36:08 2017 Stefan RittAND Trigger problems with 2-3 channels

Hi,

from our screenshots I see the following:

- you have sometimes a huge oscillation in your preamplifier. Fix this first before doing any waveform recording

- your signals are barely 20 mV, and your trigger threshold is 20 mV. The coincidence only triggers when both signals are below the trigger threshold at the same time, and the overlap must be longer than 4-5 ns. So if your signals  are not exactly in time, you won't get a coincidence trigger

Stefan

 

Rebecca Schmitz wrote:

Hello,

It seems that a coincidence with two fixed channels suddenly works. I don't know why.

Screenshot 1 shows the trigger settings for the coincidence with two channels.
Screenshot 2 shows the oscilloscope surface.
Screenshot 3 shows the configuration. In the background there is a coincidence with three channels.

In contrast to the coincidence with two channels this doesn't look good.

Rebecca

Stefan Ritt wrote:

Can you post a screenshot where I can see the channel waveforms, the configuration and the trigger settings?

Stefan

Rebecca Schmitz wrote:

Hello,

I work with the DRS4 Evaluation Board V5 and I have a problem with the software.

I have a problem with the AND trigger setting.
For this I have chosen the AND trigger function. However, when ONE channel senses an impulse, it triggers. I'm not able to see signals in the other channels, which I selected for the coincidence.

What is the cause of this? Maybe the time window?

I would like to measure a coincidence with two or three random channels. Is it possible?

Thanks for the help.

Rebecca

 

 

 

  364   Thu Aug 21 11:03:36 2014 Martin Petriska10GSps on DRS4 Evm with delay cables

 Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048).

Is it possible to use same channels to double sampling rate with paralel feeding, one channel delayed by Ts/2, for 5,12GS/s is it cca 3cm delay cable?

 

Martin

  365   Tue Aug 26 12:32:21 2014 Stefan Ritt10GSps on DRS4 Evm with delay cables

Martin Petriska wrote:

 Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048).

Is it possible to use same channels to double sampling rate with paralel feeding, one channel delayed by Ts/2, for 5,12GS/s is it cca 3cm delay cable?

 

Martin

In principle yes (you could split your signal externally and add some cable delay to one side), but it is not supported by the software. You would have to combine the data from the two channels yourself. But it won't help much. The analog bandwidth of the evaluation board is about 700 MHz. So sampling at 10 GSPS vs. 5 GSPS won't give you any additional information, since the highest frequencies in your signal will be only 700 MHz. You could as well take your 5 GSPS measurement and interpolate it with some sinc function to get exactly the same result. See here for details: http://en.wikipedia.org/wiki/Whittaker%E2%80%93Shannon_interpolation_formula 

  697   Thu May 17 13:29:34 2018 Stefan Ritt"Symmetric spikes" fixed

Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.

The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel, symmetric around sampling cell #512. See first attachment.

The reason for the spikes is the previous readout cycle. On each readout cycle, the "read bit" is clocked through all 1024 cells to switch one cell contents to the DRS4 output. At the end of the 1024 cycles, the read bit stays at its last position. The bit is carried by a metal line on the chip, which crosses all 9 channels (second attachment). This bit now influences the sampling cells below the metal line capacitively, so their contents is "pushed up" by a few mV, just like the ROFS offset does. Since the DRS sampling channels are in a snake layout, going 0-512 from left, then 512-1023 back again, the line crosses two cells in each channel, and thus the symmetric spikes.

Previously, there was a software solution for that. In the evaluation board software DRSOsc there is a button "Remove spikes" which tries to fix this in software. Although this works most of the time, it's annoying and not 100% safe. Like when the spike sits on top of a noise signal, it might not be recognized. Fixing this in hardware is however straight forwar. After the readout cycle ends, push the read bit out of the chip:

  • Address the read shift register by applying 1011b to A3:A0
  • Switch SRIN low
  • Apply 1024 clock cycles to SRCLK

This shifts the bit out of the chip, so that the next event is not affected by the read bit. The third attachment show the effect of this. The "clear cycle" increases the readout time a little bit, but depending on the application this might be worth it.

Regards,
Stefan

Attachment 1: with.png
with.png
Attachment 2: Screen_Shot_2018-05-17_at_13.30.23_.png
Screen_Shot_2018-05-17_at_13.30.23_.png
Attachment 3: without.png
without.png
  714   Mon Sep 3 11:17:26 2018 Martin Petriska"Symmetric spikes" fixed

Hi,

Is it possible to fix it by FPGA changes?  I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly put this three commands. Could you please attach app.vhd file for eval board with example how to fix ?

Regards,

Martin

 

Stefan Ritt wrote:

Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.

The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel, symmetric around sampling cell #512. See first attachment.

The reason for the spikes is the previous readout cycle. On each readout cycle, the "read bit" is clocked through all 1024 cells to switch one cell contents to the DRS4 output. At the end of the 1024 cycles, the read bit stays at its last position. The bit is carried by a metal line on the chip, which crosses all 9 channels (second attachment). This bit now influences the sampling cells below the metal line capacitively, so their contents is "pushed up" by a few mV, just like the ROFS offset does. Since the DRS sampling channels are in a snake layout, going 0-512 from left, then 512-1023 back again, the line crosses two cells in each channel, and thus the symmetric spikes.

Previously, there was a software solution for that. In the evaluation board software DRSOsc there is a button "Remove spikes" which tries to fix this in software. Although this works most of the time, it's annoying and not 100% safe. Like when the spike sits on top of a noise signal, it might not be recognized. Fixing this in hardware is however straight forwar. After the readout cycle ends, push the read bit out of the chip:

  • Address the read shift register by applying 1011b to A3:A0
  • Switch SRIN low
  • Apply 1024 clock cycles to SRCLK

This shifts the bit out of the chip, so that the next event is not affected by the read bit. The third attachment show the effect of this. The "clear cycle" increases the readout time a little bit, but depending on the application this might be worth it.

Regards,
Stefan

 

  715   Tue Sep 4 13:04:30 2018 Stefan Ritt"Symmetric spikes" fixed

Yes it's possible, but I have to find time for that. The software of the evaluation board takes care of the spikes ("remove spikes"), so I thought it's not so urgent to fix that in the FPGA (which takes me some time).

Stefan

Martin Petriska wrote:

Hi,

Is it possible to fix it by FPGA changes?  I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly put this three commands. Could you please attach app.vhd file for eval board with example how to fix ?

Regards,

Martin

 

Stefan Ritt wrote:

Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.

The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel, symmetric around sampling cell #512. See first attachment.

The reason for the spikes is the previous readout cycle. On each readout cycle, the "read bit" is clocked through all 1024 cells to switch one cell contents to the DRS4 output. At the end of the 1024 cycles, the read bit stays at its last position. The bit is carried by a metal line on the chip, which crosses all 9 channels (second attachment). This bit now influences the sampling cells below the metal line capacitively, so their contents is "pushed up" by a few mV, just like the ROFS offset does. Since the DRS sampling channels are in a snake layout, going 0-512 from left, then 512-1023 back again, the line crosses two cells in each channel, and thus the symmetric spikes.

Previously, there was a software solution for that. In the evaluation board software DRSOsc there is a button "Remove spikes" which tries to fix this in software. Although this works most of the time, it's annoying and not 100% safe. Like when the spike sits on top of a noise signal, it might not be recognized. Fixing this in hardware is however straight forwar. After the readout cycle ends, push the read bit out of the chip:

  • Address the read shift register by applying 1011b to A3:A0
  • Switch SRIN low
  • Apply 1024 clock cycles to SRCLK

This shifts the bit out of the chip, so that the next event is not affected by the read bit. The third attachment show the effect of this. The "clear cycle" increases the readout time a little bit, but depending on the application this might be worth it.

Regards,
Stefan

 

 

  716   Thu Sep 13 18:09:13 2018 Martin Petriska"Symmetric spikes" fixed

Ok, so I made it ... and Yes it works :), 

https://youtu.be/0noy4CoFoh8 

here is changed part in drs4_eval4_app.vhd

               
        when done =>
          drs_readout_state    <= spikeoff;
          drs_stat_busy        <= '0';
          drs_dpram_we1        <= '0';
          drs_write_set        <= '1';   -- set drs_write_ff in proc_drs_write
                                         -- to keep chip "warm"

 -- spike fix ELOG 697        
 
          when spikeoff => 
            o_drs_addr       <= "1011"; -- Address the read shift register by applying 1011b to A3:A0
            o_drs_srin       <= '0'; -- Switch SRIN low             
             drs_readout_state                 <= spikecycle;
             -- Apply 1024 clock cycles to SRCLK     
             drs_sr_count         <= 0;

          when spikecycle =>      
             drs_sr_count         <= drs_sr_count + 1;
             o_drs_srclk          <= not o_drs_srclk;
             if (drs_sr_count = 1024) then
                drs_readout_state <= idle;
             end if;      


        -- set-up of configuration register        

Stefan Ritt wrote:

Yes it's possible, but I have to find time for that. The software of the evaluation board takes care of the spikes ("remove spikes"), so I thought it's not so urgent to fix that in the FPGA (which takes me some time).

Stefan

Martin Petriska wrote:

Hi,

Is it possible to fix it by FPGA changes?  I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly put this three commands. Could you please attach app.vhd file for eval board with example how to fix ?

Regards,

Martin

 

Stefan Ritt wrote:

Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.

The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel, symmetric around sampling cell #512. See first attachment.

The reason for the spikes is the previous readout cycle. On each readout cycle, the "read bit" is clocked through all 1024 cells to switch one cell contents to the DRS4 output. At the end of the 1024 cycles, the read bit stays at its last position. The bit is carried by a metal line on the chip, which crosses all 9 channels (second attachment). This bit now influences the sampling cells below the metal line capacitively, so their contents is "pushed up" by a few mV, just like the ROFS offset does. Since the DRS sampling channels are in a snake layout, going 0-512 from left, then 512-1023 back again, the line crosses two cells in each channel, and thus the symmetric spikes.

Previously, there was a software solution for that. In the evaluation board software DRSOsc there is a button "Remove spikes" which tries to fix this in software. Although this works most of the time, it's annoying and not 100% safe. Like when the spike sits on top of a noise signal, it might not be recognized. Fixing this in hardware is however straight forwar. After the readout cycle ends, push the read bit out of the chip:

  • Address the read shift register by applying 1011b to A3:A0
  • Switch SRIN low
  • Apply 1024 clock cycles to SRCLK

This shifts the bit out of the chip, so that the next event is not affected by the read bit. The third attachment show the effect of this. The "clear cycle" increases the readout time a little bit, but depending on the application this might be worth it.

Regards,
Stefan

 

 

 

  106   Wed Jul 21 10:46:32 2010 Jinhong Wang ENOB of DRS

 Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip DRS4" , you define DRS4 ENOB as 1Vpp/0.35mv(RMS) = 11.5bit, where, 1Vpp is the linearity input range, and 0.35mv is the rms voltage after offset correction. What I understand is that 0.35mV is obtained from DC offset Correction, hence 11.5 bit is for DC input, am i right?  If true, what about ENOB for AC input in the whole analog bandwidth?  thanks~

  107   Wed Jul 21 10:58:20 2010 Stefan Ritt ENOB of DRS

Jinhong Wang wrote:

 Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip DRS4" , you define DRS4 ENOB as 1Vpp/0.35mv(RMS) = 11.5bit, where, 1Vpp is the linearity input range, and 0.35mv is the rms voltage after offset correction. What I understand is that 0.35mV is obtained from DC offset Correction, hence 11.5 bit is for DC input, am i right?  If true, what about ENOB for AC input in the whole analog bandwidth?  thanks~

The expression ENOB for 1Vpp/0.35mV(RMS) is wrong, but I learned this later. Now I call it SNR. The ENOB is calculated in a more complicated way, see for example http://en.wikipedia.org/wiki/ENOB. If you measure the ENOB without timing correction, it's pretty poor (in the order of 7-8 bits). This is because without timing calibration, a sine input has huge side bands, and the ENOB involves the power of your signal over the power of the side bands. If you do a proper timing calibration, you spectrum gets "sharper", and hence the ENOB increases. But I have to admit that I never measured it carefully, since we are still optimizing the timing calibration. Once we have a perfect timing calibration, I will do it and update the data sheet. 

  402   Thu Apr 9 11:46:33 2015 Felix Bachmair DRSBoard::SetTriggerSource

Hi

I have a question about the function SetTriggerSource in the class DRSBoard (DRS.h/DRS.cpp)

In the implementation there is the following comment:

// Set trigger configuration

// OR 0=CH1, 1=CH2, 2=CH3, 3=CH4, 4=EXT

// AND 8=CH1, 9=CH2, 10=CH3, 11=CH4, 12=EXT

 

What does this exactly mean? I am assuming that this are the bits which are set?

e.g

source = 1 ==> CH1

source = 4352 = 0x1100 ==> CH1 and ext

How is the AND/Or logic implemented?

When i have:

source = 0x1803 (bit 12,11,1,0)

what is the right way to set the brackets to expalin the logic?

(EXT and CH4 ) or CH2 or CH1 ?

 

Cheers Felix Bachmair

ETH Zurich

  405   Tue Apr 21 12:01:45 2015 Stefan Ritt DRSBoard::SetTriggerSource

Your first assumption is correct, e.g.

source = 00000000'00000001 = 0x0001 ==> CH1

source = 00010001'00000000 = 0x1100 ==> CH1 and EXT

So the lower byte is the "OR" block, and the upper byte is the "AND" block. Both blocks are combined via an "OR" so

source = 00011000'00000011 = 0x1803 is (EXT and CH4) OR (CH1 or CH2)

The "OR" combination between the two blocks is fixed in the firmware and cannot be changed without changing the firmware, but theoretically any logical combination between five inputs would be possible if you touch thr firmware.

/Stefan

 

Felix Bachmair wrote:

Hi

I have a question about the function SetTriggerSource in the class DRSBoard (DRS.h/DRS.cpp)

In the implementation there is the following comment:

// Set trigger configuration

// OR 0=CH1, 1=CH2, 2=CH3, 3=CH4, 4=EXT

// AND 8=CH1, 9=CH2, 10=CH3, 11=CH4, 12=EXT

 

What does this exactly mean? I am assuming that this are the bits which are set?

e.g

source = 1 ==> CH1

source = 4352 = 0x1100 ==> CH1 and ext

How is the AND/Or logic implemented?

When i have:

source = 0x1803 (bit 12,11,1,0)

what is the right way to set the brackets to expalin the logic?

(EXT and CH4 ) or CH2 or CH1 ?

 

Cheers Felix Bachmair

ETH Zurich

 

  257   Sun May 26 13:08:52 2013 tmiron alon 

Hallo,
I'm using DRS4 Evaluation Board Rev 4.0 and I'm trying to change the output of the samples to be an average of  #  measurements (1000 or even more)
during the process I have encountered some difficulties I hope you will be able to help me  with:

1. the DRS chip have 8 channels but the Evaluation board have only 4 channels. does the default mode of the DRS in the Evaluation Board is 1024 bins for each channel or 2048?

2. in the readout mode, does it samples all the 1024 bins waveform from a channel and then move to the next one, or after each bin it move to the next channel?

3. In the file "drs4_eval4_app.vhd", I have a problem finding the names of the signals that represents the registers bits which tell me what is the number of the bin (1-1024) the ADC is reading from the DRS, and the signals

that represents registers A0-A3. can you send me their names? 

 

4. In another matter- is the -0.5V to 0.5V is the  upper and lower  limit of the input (or just a working range), and if not what is the limit for AC?  is there a fuse on the board in case of overload from the input? (I didn't see  it in the User's Manual, but I didn't know if you will mention it there in case there is one).

thanks in advance and have a nice day,

Tmiron

  258   Fri Jun 7 10:22:48 2013 Stefan Ritt 

tmiron alon wrote:

Hallo,
I'm using DRS4 Evaluation Board Rev 4.0 and I'm trying to change the output of the samples to be an average of  #  measurements (1000 or even more)
during the process I have encountered some difficulties I hope you will be able to help me  with:

1. the DRS chip have 8 channels but the Evaluation board have only 4 channels. does the default mode of the DRS in the Evaluation Board is 1024 bins for each channel or 2048?

2. in the readout mode, does it samples all the 1024 bins waveform from a channel and then move to the next one, or after each bin it move to the next channel?

3. In the file "drs4_eval4_app.vhd", I have a problem finding the names of the signals that represents the registers bits which tell me what is the number of the bin (1-1024) the ADC is reading from the DRS, and the signals

that represents registers A0-A3. can you send me their names? 

 

4. In another matter- is the -0.5V to 0.5V is the  upper and lower  limit of the input (or just a working range), and if not what is the limit for AC?  is there a fuse on the board in case of overload from the input? (I didn't see  it in the User's Manual, but I didn't know if you will mention it there in case there is one).

thanks in advance and have a nice day,

Tmiron

1. All 8 channels are read out, but only 4 are displayed in the oscilloscope.

2. It reads all 1024 bins from a channel, then switch to the next channel.

3. The ADC readout happens in lines 1576+. The register for the sample count is drs_sample_count, and the signal for the address is drs_addr.

4. The evaluation board manual explicitly mentions the maximum allowed input range on page 5.

/Stefan 

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