DRS4 Forum
  DRS4 Discussion Forum, Page 4 of 44  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
    Reply  Tue Feb 15 12:02:29 2022, Stefan Ritt, Cannot trigger on pulses, have to trigger on undershoot 
Entry  Thu Nov 14 11:39:06 2013, Schablo, Cascading of channels  
    Reply  Thu Nov 14 12:51:56 2013, Stefan Ritt, Cascading of channels  2048_mode.pdf
    Reply  Thu Nov 21 14:35:57 2013, Schablo, Cascading of channels  
    Reply  Thu Nov 21 14:45:56 2013, Stefan Ritt, Cascading of channels  
Entry  Mon Aug 31 16:44:12 2020, Hans Steiger, Channel Cascading 
    Reply  Mon Aug 31 17:17:30 2020, Stefan Ritt, Channel Cascading Screenshot_2020-08-31_at_16.52.28_.png
Entry  Fri Nov 18 05:52:45 2016, Kurtis Nishimura, Channel offsets in GetTime() offsetInstructions.png
    Reply  Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime() 
Entry  Wed Feb 27 13:47:32 2013, Georg Winner, Chip Test - Cell Error 
    Reply  Wed Mar 6 13:08:03 2013, Stefan Ritt, Chip Test - Cell Error 
Entry  Wed Oct 15 10:14:32 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
    Reply  Wed Oct 15 10:52:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ 
    Reply  Wed Oct 15 11:34:43 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
    Reply  Wed Oct 15 12:15:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ drs_exam_multi.cpp
    Reply  Fri Apr 17 10:07:38 2015, Simon Weingarten, Clock settings in daisy chain DAQ 
    Reply  Mon Apr 20 13:08:24 2015, Stefan Ritt, Clock settings in daisy chain DAQ 
Entry  Tue Jan 12 17:57:03 2016, Jack Bargemann, Compiling DRS-exam 
    Reply  Tue Jan 12 21:02:31 2016, Stefan Ritt, Compiling DRS-exam 
Entry  Wed Oct 23 17:56:26 2019, John Jendzurski, Computing corrected time from binary data...what is t_0,0? Screenshot.png
ELOG V3.1.4-bcd7b50