 Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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 Wed Mar 3 17:36:31 2010, Hao Huan, Initialization of the Domino Circuit
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Hi Stefan,
I read in the datasheet that every time after power up the Domino wave in DRS4 needs to be started and stopped once to initialize
the Domino circuit. However in your firmware it seems the chip immediately goes into the idle state after reset. Is that Domino circuit initialization |
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Thu Mar 4 19:14:10 2010, Hao Huan, Readout of DRS Data
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Hi Stefan,
thanks to your help I can now successfully keep the Domino wave running at a stable frequency and maintain the channel cascading
information in the Write Shift Register. (Since you told me WSR always reads and writes at the same time, I think I need to rewrite the information back |
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Fri Mar 5 23:29:04 2010, Hao Huan, Readout of DRS Data
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Hao Huan wrote:
Hi Stefan, |
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Tue Mar 9 23:28:45 2010, Hao Huan, Serial Interface Frequency of the DRS Chip
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Hi Stefan,
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation board firmware SRCLK is
toggled at rising edges of the internal 33MHz clock, i.e. the frequency of SRCLK itself is 16.5MHz instead. Is that frequency better than 33MHz? |
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Thu Mar 11 21:37:32 2010, Hao Huan, Input Bandwidth of the DRS Chip
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Hi Stefan,
I read in the DRS datasheet that the input bandwidth if 950MHz. However, it also says the output bandwidth in the transparent
mode is 50MHz. Since in the transparent mode the input is routed to the output, does it mean the input bandwidth also gets reduced in the transparent mode? |
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Thu Mar 18 21:38:10 2010, Hao Huan, Serial Interface Frequency of the DRS Chip
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Stefan Ritt wrote:
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Sun Mar 21 02:03:44 2010, Hao Huan, PLL Loop Filter Configuration
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Hi Stefan,
in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF. If I want to run the Domino
wave nominally at 1GHz, i.e. with a reference clock frequency around 0.5MHz, is there any recommended loop filter configuration? Is the setup of the evaluation |
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Tue Mar 30 22:57:34 2010, Hao Huan, ROFS Configuration
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Hi Stefan,
according to the DRS4 datasheet, if we want an input range centered around U0, the ROFS should be 1.55V-U0. However when I read
the codes of the evaluation board application, ROFS seems to be 1.6V-1.25*U0 where the coefficient 1.25 is said to come from sampling cell charge injection |
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Fri Apr 9 17:14:45 2010, Hao Huan, Baseline Variation In Data
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Hi Stefan,
when I sample a constant input with the DRS 4 chip, there was a baseline variation showing up as a saw-tooth pattern which grows
with the absolute value of the differential input. Do you think this is the kind of baseline variation mentioned in the evaluation board manual, i.e. coming |
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Thu May 13 19:14:27 2010, Hao Huan, DVDD Problem of DRS 4
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Hi Stefan,
on our board some DRS chips draw a lot of current through DVDD after power-up and heat up significantly--it is true that our
board doesn't have weak pull-down resistors at DENABLE and DWRITE output pins of FPGA, so this problem might have been caused by that, but a reinitialization |
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Tue May 18 01:47:59 2010, Hao Huan, DVDD Problem of DRS 4
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Stefan Ritt wrote:
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Wed May 19 02:24:12 2010, Hao Huan, DVDD Problem of DRS 4
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Stefan Ritt wrote:
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Wed May 26 19:18:09 2010, Hao Huan, High Frequency Input for DRS
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Hi Stefan,
I read in the DRS datasheet that the bandwidth for the transparent mode OUT+ is only 200MHz which I think cannot be improved
by any active input buffer; so if you want to operate the chip for really high frequency input, would it be better to feed on-board discriminators not |
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Sun Oct 23 23:32:28 2011, Hao Huan, Phase Shift for ADC Readout
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Dear Dr. Ritt,
In the DRS 4 datasheet it is recommended to sample the analog output of the chip after 8~10 ns of the SRCLK edge for it to stablize
and thus a phase shift between SRCLK and the ADC sampling clock is necessary. However in the latest version of the evaluation board firmware the phase-shifted |
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Wed Dec 14 00:44:37 2011, Hao Huan, Synchronization Delay in the Firmware for 8051 Controller
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Hi Stefan,
I have a question regarding the DRS 4 evaluation board firmware for the 8051 controller embedded in the CY7C68013 USB chip:
on the board the controller is running at 12 MHz and the FIFO interface of the USB chip is running at 30 MHz, so the number of delay cycles for synchronization |
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Mon Apr 5 17:50:39 2010, Heejong Kim, version 1.2 evaluation board with firmware 13279?
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Hi, Stefan,
I found that my collaborator bought 2 older version of evaluation board before.
They are the version 1.2 in plastics case with firmware
13191.
Can I upgrade the firmware from 13191 to 13279?
I'm wondering if the older version of evaluation board is working with firmware 13279.
Thanks,
Heejong
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Mon Apr 5 17:57:41 2010, Heejong Kim, Simple example application to read a DRS evaluation board
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Stefan Ritt wrote:
Several people asked for s simple application to guide them in writing their own application to read out |