DRS4 Forum
  DRS4 Discussion Forum, Page 10 of 45  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
    Reply  Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4 
    Reply  Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4 
    Reply  Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4 
Entry  Wed Mar 3 17:36:31 2010, Hao Huan, Initialization of the Domino Circuit 
Entry  Thu Mar 4 19:14:10 2010, Hao Huan, Readout of DRS Data 
    Reply  Fri Mar 5 23:29:04 2010, Hao Huan, Readout of DRS Data 
Entry  Tue Mar 9 23:28:45 2010, Hao Huan, Serial Interface Frequency of the DRS Chip 
Entry  Thu Mar 11 21:37:32 2010, Hao Huan, Input Bandwidth of the DRS Chip 
    Reply  Thu Mar 18 21:38:10 2010, Hao Huan, Serial Interface Frequency of the DRS Chip 
Entry  Sun Mar 21 02:03:44 2010, Hao Huan, PLL Loop Filter Configuration 
Entry  Tue Mar 30 22:57:34 2010, Hao Huan, ROFS Configuration 
Entry  Fri Apr 9 17:14:45 2010, Hao Huan, Baseline Variation In Data 
Entry  Thu May 13 19:14:27 2010, Hao Huan, DVDD Problem of DRS 4 
    Reply  Tue May 18 01:47:59 2010, Hao Huan, DVDD Problem of DRS 4 
    Reply  Wed May 19 02:24:12 2010, Hao Huan, DVDD Problem of DRS 4 
Entry  Wed May 26 19:18:09 2010, Hao Huan, High Frequency Input for DRS 
Entry  Sun Oct 23 23:32:28 2011, Hao Huan, Phase Shift for ADC Readout 
Entry  Wed Dec 14 00:44:37 2011, Hao Huan, Synchronization Delay in the Firmware for 8051 Controller 
Entry  Mon Apr 5 17:50:39 2010, Heejong Kim, version 1.2 evaluation board with firmware 13279? 
    Reply  Mon Apr 5 17:57:41 2010, Heejong Kim, Simple example application to read a DRS evaluation board 
ELOG V3.1.5-fe60aaf