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Fri Feb 26 20:32:25 2021, Stefan Ritt, Trouble getting PLL to lock        Fri Feb 26 21:24:39 2021, Tom Schneider, Trouble getting PLL to lock        Fri Feb 26 22:12:58 2021, Stefan Ritt, Trouble getting PLL to lock        Fri Feb 26 22:52:13 2021, Tom Schneider, Trouble getting PLL to lock        Thu Mar 4 21:36:14 2021, Tom Schneider, Trouble getting PLL to lock        Fri Mar 5 09:39:42 2021, Stefan Ritt, Trouble getting PLL to lock        Fri Dec 24 03:13:32 2021, Lynsey, Trouble getting PLL to lock    Fri Nov 3 12:11:14 2017, Håkan Wennlöf, Triggering using AND        Fri Nov 3 13:28:04 2017, Stefan Ritt, Triggering using AND    Thu Jan 14 21:49:37 2016, Chris Thompson, Triggering of DRS4 in the fastest sampling mode        Fri Jan 15 08:09:00 2016, Stefan Ritt, Triggering of DRS4 in the fastest sampling mode    Thu Jul 6 15:10:48 2017, Esperienza Giove, Trigger setting (AND AND) OR (AND AND)        Fri Jul 7 10:31:47 2017, Stefan Ritt, Trigger setting (AND AND) OR (AND AND)    Thu Mar 31 19:30:26 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal        Thu Mar 31 19:35:06 2016, Stefan Ritt, Trigger on the And of a positive and negative signal        Thu Mar 31 19:44:38 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal        Thu Mar 31 20:34:25 2016, Stefan Ritt, Trigger on the And of a positive and negative signal        Thu Mar 31 20:38:05 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal        Thu Mar 31 20:48:00 2016, Chris Thompson, Trigger on the And of a positive and negative signal        Fri Apr 1 01:30:40 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal

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