| ID |
Date |
Author |
Subject |
Text |
 |
|
814
|
Fri Feb 26 20:32:25 2021 |
Stefan Ritt | Trouble getting PLL to lock | Can you post a scope trace of your refclk
together with DTAP, DSPEED and DENABLE?
|
|
|
815
|
Fri Feb 26 21:24:39 2021 |
Tom Schneider | Trouble getting PLL to lock | Probe capacitance makes that tricky - if
I put my probe on DSPEED, I see that it starts
at approx. 2.5V then gradually decreases |
|
|
816
|
Fri Feb 26 22:12:58 2021 |
Stefan Ritt | Trouble getting PLL to lock | Sounds to me like your REFCLK is not getting
through or your PLL loop is open. Could be
a bad solder connection. Try to measure signals |
|
|
817
|
Fri Feb 26 22:52:13 2021 |
Tom Schneider | Trouble getting PLL to lock | Thats not a simple modification to my PCB,
but I'll give it a try. Thanks
for your help |
|
|
818
|
Thu Mar 4 21:36:14 2021 |
Tom Schneider | Trouble getting PLL to lock | I found the problem, and it had nothing
to do with the CMOS clock input. As
it turns out, even though I was using the |
|
|
819
|
Fri Mar 5 09:39:42 2021 |
Stefan Ritt | Trouble getting PLL to lock | That probably depends on the way your FPGA
boots. If the SRCLK signal goes high after
the SRIN - even a few ns - you might clock |
|
|
854
|
Fri Dec 24 03:13:32 2021 |
Lynsey | Trouble getting PLL to lock | I also design the circuit myself. Our problem
is the same. Can we communicate？
|
|
|
636
|
Fri Nov 3 12:11:14 2017 |
Håkan Wennlöf | Triggering using AND | Hi!
I'm using the DRSOsc program,
and I have a question that I need a bit clarified; |
|
|
637
|
Fri Nov 3 13:28:04 2017 |
Stefan Ritt | Triggering using AND | Think about: How would you make a coincidence
(AND) between two edges? Since an edge is
infinitesimally small, there is no way to |
|
|
475
|
Thu Jan 14 21:49:37 2016 |
Chris Thompson | Triggering of DRS4 in the fastest sampling mode | I am attempting to use the DRS4 to measure
the timing resolution of a pair of SensL
silicon photomultipliers (SiPM). In order |
|
|
476
|
Fri Jan 15 08:09:00 2016 |
Stefan Ritt | Triggering of DRS4 in the fastest sampling mode | Hi Chris,
if you ever used an oscilloscope,
you might be familar with the button controlling |
|
|
621
|
Thu Jul 6 15:10:48 2017 |
Esperienza Giove | Trigger setting (AND AND) OR (AND AND) | Hello there,
is it possible to setup trigger
in double AND configuration (a pair in and |
|
|
622
|
Fri Jul 7 10:31:47 2017 |
Stefan Ritt | Trigger setting (AND AND) OR (AND AND) | Unfortunately not with the current firmware.
Stefan
|
|
|
487
|
Thu Mar 31 19:30:26 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | I would like to be able to trigger in this
fashon: channel 0 > 0.1 and. channel
1< -0.1, because I have a positive |
|
|
488
|
Thu Mar 31 19:35:06 2016 |
Stefan Ritt | Trigger on the And of a positive and negative signal | No. You have to use an inverter for one
of your signals.
Stefan |
|
|
489
|
Thu Mar 31 19:44:38 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | Ok, thanks! do you know an easy in-line
inverter like mini-circuit or digikey?
Can also redesign the detector I gues to |
|
|
490
|
Thu Mar 31 20:34:25 2016 |
Stefan Ritt | Trigger on the And of a positive and negative signal | Here is one (SI 100): https://www.picoquant.com/products/category/accessories/adapters-splitters-cables-various-accessories-for-photon-counting-setups
|
|
|
491
|
Thu Mar 31 20:38:05 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | Thanks, that looks just fine.
|
|
|
492
|
Thu Mar 31 20:48:00 2016 |
Chris Thompson | Trigger on the And of a positive and negative signal | I needed a fast pulse inverter in order
to feed signals from the recent SensL SiPMs
into a conventional CFD which only accepted |
|
|
493
|
Fri Apr 1 01:30:40 2016 |
Abaz Kryemadhi | Trigger on the And of a positive and negative signal | Hi Chris,
I am looking at Sensl SiPMs
as well, can you send the part number |
|