ID |
Date |
Author |
Subject |
Text |
 |
806
|
Thu Dec 17 11:31:34 2020 |
Stefan Ritt | drs sources on github? | Not github, but bitbucket: https://bitbucket.org/ritt/drs4eb/src/master/
But development kind of stalled, so there |
|
808
|
Wed Jan 20 17:37:51 2021 |
Stefan Ritt | drs4 persistence | The chip itself can only sample a single
waveform, that must be done in the attached
software. The current DRSOscilloscope software |
|
810
|
Fri Feb 26 08:52:50 2021 |
Stefan Ritt | DRS spike removal for multiple waveforms | Just look at the definition of the function
below, all parameters are explained there.
In meantime we have a firmware fix to avoid |
|
812
|
Fri Feb 26 17:59:14 2021 |
Stefan Ritt | Trouble getting PLL to lock | I guess you mean "1 MHz clock at REFCLK+",
and not CLKIN, there is no CLKIN, just a
SRCLK, but that is someting else! |
|
814
|
Fri Feb 26 20:32:25 2021 |
Stefan Ritt | Trouble getting PLL to lock | Can you post a scope trace of your refclk
together with DTAP, DSPEED and DENABLE?
|
|
816
|
Fri Feb 26 22:12:58 2021 |
Stefan Ritt | Trouble getting PLL to lock | Sounds to me like your REFCLK is not getting
through or your PLL loop is open. Could be
a bad solder connection. Try to measure signals |
|
819
|
Fri Mar 5 09:39:42 2021 |
Stefan Ritt | Trouble getting PLL to lock | That probably depends on the way your FPGA
boots. If the SRCLK signal goes high after
the SRIN - even a few ns - you might clock |
|
821
|
Wed Apr 7 08:26:12 2021 |
Stefan Ritt | Unexpected noise in muxout: t_samp related? | Dear Sean,
noise in transparent mode comes
from some coupling to your system clock. |
|
824
|
Fri Apr 9 20:55:28 2021 |
Stefan Ritt | Unexpected noise in muxout: t_samp related? | If you do the cell calibration correctly,
your noise should be ~0.4 mV. You seem to
be 2-3x larger. The periodic negative spikes |
|
825
|
Fri Apr 9 21:38:59 2021 |
Stefan Ritt | Spikes/noise sensitive to clock settings? | elog:824
|
|
828
|
Wed May 5 10:12:44 2021 |
Stefan Ritt | recording only timestamp and amplitude and/or filesize maximum | The maximum file size depends on the underlying
linux file system. Common values are 4-16
GBytes. |
|
830
|
Mon Aug 9 12:50:31 2021 |
Stefan Ritt | C code to read the 4 channel with external trigger | Sorry the late reply, I was on vacation.
Here are some answers:
1. I'm sorry I can't help |
|
834
|
Sat Sep 18 15:47:50 2021 |
Stefan Ritt | how to acquire the stop channel with 2x4096 cascading | The problem must be on your side, since
the Write Shift Register readout works in
other applications with the DRS4 chip. So |
|
835
|
Sat Sep 18 15:48:30 2021 |
Stefan Ritt | drs_exam_multi with non-v4 boards, default configuration | Hi,
please note the the evaluation
board is what it says, a board to evaluate |
|
838
|
Thu Oct 14 15:25:07 2021 |
Stefan Ritt | livetime (or deadtime) of DRS4 evaluation board | The one thing you can do easily is to look
at the scaler values. If one channel counts
all physical events, and you have all read |
|
840
|
Thu Oct 14 18:42:31 2021 |
Stefan Ritt | livetime (or deadtime) of DRS4 evaluation board | I would say not exactly, but it's a
good approximation.
|
|
844
|
Tue Oct 26 12:00:51 2021 |
Stefan Ritt | External trigger and drs_exam | 1. Why should your waveform start from
0 to 5ns? I don't get your point. Whenever
you trigger a readout, you get a 200ns wide |
|
845
|
Tue Oct 26 12:02:56 2021 |
Stefan Ritt | Trigger multiple boards independently | Unfortunately an independent operation
from a single computer is not supported by
the software. You can try to modify the drs_exam |
|
848
|
Wed Oct 27 08:11:42 2021 |
Stefan Ritt | Trigger multiple boards independently | I'm not sure if the rate would go up
to 2 kHz (not 2 GHz!). Depends how the USB
hub is designed. What you can do however |
|
852
|
Tue Nov 16 08:51:14 2021 |
Stefan Ritt | V3 board, only one channel works, all components at each channel input working | A V3 boards is already 10 years old and
out of warranty. The software has no configuration
to turn channels off except the channel buttons |
|