 Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed 
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Dear DRS4 team,
On page 3 of the data sheet, Table 1. for readout speed a typical value of 10 MHz is specified, but in the comment column it notes optimal performance
achieved at 33 MHz. |
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Mon Nov 5 17:17:08 2018, Sean Quinn, Pi attenuator on eval board inputs?
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Dear DRS4 team,
I am curious about this part of the circuit: |
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Wed Apr 7 03:29:39 2021, Sean Quinn, Unexpected noise in muxout: t_samp related?
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Dear DRS4 team,
I'm experiencing some issues that seem to be isolated to the ASIC, and would like to understand if we are doing something wrong. There are
several items to address in the post. |
 Fri Apr 9 20:22:13 2021, Sean Quinn, Unexpected noise in muxout: t_samp related?
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Hi Stefan,
Thanks much for the quick reply. Ok, yes, things do seem ok after the offset calibration. I am running into some other issues I could use your |
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Fri Apr 9 20:29:45 2021, Sean Quinn, Spikes/noise sensitive to clock settings?
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Dear DRS4 team,
I'm trying to troubleshoot some odd spike behavior. If I run the ADC and SR CLK at 16 MHz (behavior also seen at 33 MHz) we get very noisy
data (post-calibration) with periodic spikes. |
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Fri Apr 9 21:56:54 2021, Sean Quinn, Unexpected noise in muxout: t_samp related?
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Yes, there is some systematic board noise on this prototype, unfortunately
Ok, then it seems the other post I made might still belong in this thread after all. |
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Thu Nov 14 11:39:06 2013, Schablo, Cascading of channels
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Hello, I want use cascading of channels for 2048 cell - SetChannelConfig(0,8,4), but i can't understand how . Please, help me. Where i can
dowload 2048_mode.ppt. (I found information about this file in DRS.cpp (3445 line "/ combine |
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Thu Nov 21 14:35:57 2013, Schablo, Cascading of channels
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Stefan Ritt wrote:
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Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study
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We have been using DRS4 IC in our design for quite some time and it is giving good performance.
Till now we were using Domino wave frequency as 1 GSPS by use of reference clock to DRS4 and internal PLL of DRS4. Recently we tried to use 4GSPS
by modifying the reference clock. |
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Wed May 11 15:48:57 2016, SANDJONG Saturnin Orly, Probléme de Calibration de la DRS4
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Bonjour, Je suis en stage dans un laboratoire ou on utilise pour echantillonnage des données, une cartes DRS4 5GSPS avec 1024 cell, mon probléme
réside dans la partie Calibration en tension selon l'article "Novel Calibration Method for Switched Capacitor Arrays Enables Time
Measurements with Sub-Picosecond Resolution". |
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Sat Feb 19 17:25:29 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards
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Dear sir,
We have two evaluation boards of DRS4. We would like to use 8 inputs to be recorded on a trigger and we would like to find the relative time difference
of inputs. So is it possible to synchronize the sampling frequency of the two evaluation boards. |
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Mon Feb 21 12:42:33 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards
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Stefan Ritt wrote:
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Mon Feb 15 19:43:34 2010, Ron Grazioso, Problem reading oscilloscope binary waveform output
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I have saved some waveforms using the oscilloscope application in both binary and xml. I can see that the xml file gives me proper data values
but when I try to read the binary file using IDL, it does not seem correct. This is a screen shot of the pulse I saved: |
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Thu Apr 10 14:45:12 2014, Roman Gredig, DRS4 Evalboard V5 with Windows7Pro64bit
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Dear Stefan
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Thu Jun 12 12:40:03 2014, Roman Gredig, DRS eval bord v5 Timing
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Dear Stefan
I have two questions concerning the best time resolution with the DRS V5 eval board.
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Wed Aug 13 20:17:19 2014, Roman Gredig, binary files time calibration header in drs-5.0.2
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Dear Stefan
I have a problem considering binary data files.
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Tue Aug 26 14:16:26 2014, Roman Gredig, binary files with more than 4 drs board ver. 5.0.2
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Dear Stefan
after having some problems with writing binary files with more than 4 drs boards (in multiboard-mode) I might
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Wed Mar 7 22:49:38 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp
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Hello,
We have been using the DRS4 evaluation board (S/N 2636) that works with the scope application. However we are trying to run the DRS4 evaluation
board remotely by modifying the drs_exam.cpp to acquire and store data continuously. |
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Thu Mar 8 22:54:20 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp
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We found a way to solve the previous problem, but right now when we try to set the input range only -0.5 to 0.5 is working. When we set the function
"SetInputRange(0.5)" for 0 to 1V the output is all zeros and with "SetInputRange(0.45)" we just get all the outputs -49.9mV.
What does that means? How to fix? |
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Thu Feb 22 01:21:11 2024, Rod McInnis, Simulation of FPGA
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Hello:
A bit of background: I am working on a project that is utilizing the DRS4 Evaluation board as a prototype platform for a dedicated, special
use capture. We will only be utilizing one channel of the ADC capture, and the 1024 samples is more than enough. |