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Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed    Mon Nov 5 17:17:08 2018, Sean Quinn, Pi attenuator on eval board inputs?    Wed Apr 7 03:29:39 2021, Sean Quinn, Unexpected noise in muxout: t_samp related?        Fri Apr 9 20:22:13 2021, Sean Quinn, Unexpected noise in muxout: t_samp related?    Fri Apr 9 20:29:45 2021, Sean Quinn, Spikes/noise sensitive to clock settings?        Fri Apr 9 21:56:54 2021, Sean Quinn, Unexpected noise in muxout: t_samp related?    Thu Nov 14 11:39:06 2013, Schablo, Cascading of channels         Thu Nov 21 14:35:57 2013, Schablo, Cascading of channels     Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study    Wed May 11 15:48:57 2016, SANDJONG Saturnin Orly, Probléme de Calibration de la DRS4    Sat Feb 19 17:25:29 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards        Mon Feb 21 12:42:33 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards    Mon Feb 15 19:43:34 2010, Ron Grazioso, Problem reading oscilloscope binary waveform output    Thu Apr 10 14:45:12 2014, Roman Gredig, DRS4 Evalboard V5 with Windows7Pro64bit    Thu Jun 12 12:40:03 2014, Roman Gredig, DRS eval bord v5 Timing    Wed Aug 13 20:17:19 2014, Roman Gredig, binary files time calibration header in drs-5.0.2    Tue Aug 26 14:16:26 2014, Roman Gredig, binary files with more than 4 drs board ver. 5.0.2    Wed Mar 7 22:49:38 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp        Thu Mar 8 22:54:20 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp    Thu Feb 22 01:21:11 2024, Rod McInnis, Simulation of FPGA

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