| ID |
Date |
Author |
Subject |
Text |
 |
|
918
|
Thu May 8 23:23:19 2025 |
Jonathan Bradshaw | Clarification of full channel readout | Hi all
We're working on a new product
using the DRS4 IC, and want to do a full |
|
|
919
|
Thu May 8 23:41:03 2025 |
Jonathan Bradshaw | Handling of Write Shift Register and Write Config Register | Hi all
We're building a product which
will use two different operating modes; firstly |
|
|
903
|
Wed Oct 25 19:44:25 2023 |
John Westmoreland | WaveDREAM Design | Hello All,
Are there any design resources
available for the WaveDREAM PCBA's? |
|
|
905
|
Wed Oct 25 19:52:33 2023 |
John Westmoreland | WaveDREAM Design | Stefan,
Oh, didn't realize that.
Thanks! |
|
|
781
|
Wed Oct 23 17:56:26 2019 |
John Jendzurski | Computing corrected time from binary data...what is t_0,0? | In the equations for computing the corrected
time for channels other than channel 1, does
anyone know what the term t0,0 refers |
|
|
15
|
Fri Oct 16 09:51:03 2009 |
Jinhong Wang | DSR4 Full Readout Mode | Hello Mr. Stefan Ritt
In DSR4 DATASHEET Rev.0.8 Page13, I noticed |
|
|
17
|
Mon Oct 19 09:06:43 2009 |
Jinhong Wang | BIAS Pin of DRS4 | Dear Mr. Stefan Ritt.
Thank u for your timely response on "DSR4 |
|
|
19
|
Mon Oct 19 11:26:29 2009 |
Jinhong Wang | output common mode voltage of DRS4 | Hello Mr.
Stifan.Ritt
In
the DSR4 datasheet, it is mentioned that |
|
|
21
|
Fri Oct 30 03:31:54 2009 |
Jinhong Wang | outline dimension of DRS4 | |
|
|
23
|
Mon Dec 14 10:14:16 2009 |
Jinhong Wang | Trigger of DRS4 | Dear Mr. S. Ritt
The
following is my confusion about the |
|
|
25
|
Mon Dec 21 10:17:05 2009 |
Jinhong Wang | Trigger of DRS4 |
|
|
|
27
|
Tue Dec 22 01:30:55 2009 |
Jinhong Wang | Trigger of DRS4 |
|
|
|
78
|
Wed May 12 11:47:39 2010 |
Jinhong Wang | DRS4 chip model |
|
|
|
91
|
Fri Jun 18 11:31:20 2010 |
Jinhong Wang | DVDD Problem of DRS 4 |
|
|
|
93
|
Sat Jun 19 10:09:18 2010 |
Jinhong Wang | DVDD Problem of DRS 4 |
|
|
|
94
|
Tue Jun 22 10:50:19 2010 |
Jinhong Wang | Reset of DRS4 | Hi Stefan,
I found
DRS draw a lot of current when applied Reset |
|
|
96
|
Tue Jun 22 11:29:26 2010 |
Jinhong Wang | Reset of DRS4 |
|
|
|
98
|
Tue Jun 22 11:37:42 2010 |
Jinhong Wang | Reset of DRS4 |
|
|
|
104
|
Mon Jul 19 12:07:04 2010 |
Jinhong Wang | Fixed Patter Timing Jitter | Hi Stefan, can you give some suggestions
on determination of fixed pattern timing
jitter of DRS4? Thanks~ |
|
|
106
|
Wed Jul 21 10:46:32 2010 |
Jinhong Wang | ENOB of DRS | Hi, Stefan, I see in your ppt "Design
and performance of 6 GSPS waveform digitizing
chip DRS4" , you define DRS4 ENOB as |
|