 Thu May 12 05:18:47 2016, Yu, Problem For Software Download
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Hi
I can't download the software for windows on this website 'www.psi.ch/drs/software-download', there is some mistake when i
click on download. |
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Wed Feb 15 18:08:13 2012, Yuji Iwai, Evaluation Board v4 Trigger/Clock Connectors
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| Quick question - what type of connectors are used for the trigger and clock in/out on the v4 eval board? |
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Fri Feb 22 11:46:17 2013, Yury Golod, DRS4 trigger, different polarity
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Normal
0
MicrosoftInternetExplorer4
/* Style Definitions */
table.MsoNormalTable
{mso-style-name:"Обычная |
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Sun Aug 27 12:44:16 2017, Yuvaraj Elangovan, DRS4 version Support
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| Hi i am using DRS4 Eval Board V2, How to acquire data to a bin file using it. |
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Mon Jul 14 19:03:05 2014, Yves Bianga, change cascading from 1024 to 2048 bins for each input channel
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Hello,
I want to ask whether it is possible to modify a Evaluation Board 5.0 from 1024 to 2048 cells for each of the 4 input channels.
On
the rev50 manual at page 31 I found an option to connect the 4 unused channels by setting 8 solder bridges.
The source code for controlling |
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Tue Aug 28 17:52:45 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp
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Hi,
I found an old thread regarding a fix for DOScreen.cpp for DRS-3.1.0, that fixes an "ambiguous overload problem." Currently when I attempt
to build the drs-4.0.0, I get this similar error: |
 Wed Aug 29 16:42:42 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp
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Stefan Ritt wrote:
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Wed Aug 29 16:57:49 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp
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Stefan Ritt wrote:
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Thu Oct 4 20:50:36 2012, Zach Miller, DRS5
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Hi,
Our group had previously heard that a "DRS-5.0" might be on the horizon and that it may have ethernet capabilities as well as 16-input
channels (we heard this when ordering the DRS-4). Is this still in the works and accurate information? If so, is there a rough estimate to the "release |
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Thu Oct 4 21:07:27 2012, Zach Miller, DRS5
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Stefan Ritt wrote:
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Mon Oct 31 09:15:02 2011, Zhongwei Du, How to link PMT
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I want to measure the signal from PMT . But it is a current signal, should i just put a series resistance, or use a amplifier to convert it to voltage
signal before drs4?
Can you give me some advice ? |
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Sat Feb 4 11:59:26 2012, Zhongwei Du, what sort of detectors for physical experiment the DRS4 used?
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Hello.
We are designing a waveform sampling board for Si strip array detector ,whose rise time is less than 10 ns, which makes we doubt whether the
DRS4 can do more accurate than traditional charge integral circuit for charge measuring. |
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Tue Dec 4 09:24:22 2012, Zhongwei Du, Question of drs4 using
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When Denable and Dwrite is high , the voltage of PLLOUT is 0 V. And the Dtap is turn high with no delay when the Denable turns high.
After power up and configuration(the WSR,WCR,CR are all set to 11111111), the readout data is no change whenever the input analog signal and rofs,bias,oofs
changes. I have test useing the DAC to supply the Dspeed voltage, and change a new DRS4 chip, but all is the same. The readout data is strange : the first |
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Tue Dec 4 09:50:11 2012, Zhongwei Du, Question of drs4 using
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Stefan Ritt wrote:
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Wed Dec 30 14:28:33 2009, aliyilmaz, normal_mode_in_drs_exam.cpp
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Dear Mr. S. Ritt
i am Ms. student , am working with your DRS4 board to calculate the time of flight of the cosmic particle which passes
trough the hodoscope . i see the signals at scope , which is negative (i don't want to take positive side of the signal). |
Tue Jul 23 22:31:08 2013, alonzi, Evaluation Board Behavior 
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Working with the DRS evaluation board we noticed some funny behavior: See attatchment 1. In about 1% of scope traces we see the first and last bin take
on a value substantially different from the baseline, note the small spikes on the end of the traces. These spikes occur across all channels and either
appear in all channels or in none. Attachment two shows what several thousand scope traces look like. You can clearly see that some of the traces are offset |
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Tue Jul 23 22:42:31 2013, alonzi, Evaluation Board Behavior
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Stefan Ritt wrote:
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Mon Aug 29 09:36:34 2016, benjamin legeyt, increment write config register on the fly?
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Hello,
I have a question about using the write config register to enable/disable sampling on the fly. I am looking to instrument an experiment
at EPFL where multiple short events need to be captured during a 20us period followed by an 80us quiet period during which we could read out the chip. |
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Mon Aug 29 12:18:49 2016, benjamin legeyt, increment write config register on the fly?
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If I may trouble you for a little more information, the critical point then is that there should not be any zeroes in the write config register
while the sampling is active? In case it was unclear I would only be reading out once sampling was stopped (dwrite = 0).
As for the readout, I know that I would have to read out all 1024 samples each time, and keep track of where each channel stopped in the FPGA. |
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Thu Jan 25 05:24:05 2018, chen wenjun, problem with the drscl(drs507)
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Hi! Stefan:
when I change a new computer(win7,64bit),I meet a problem that the drscl app cannot found the board! It shows"USB successfully scanned,but
no boards found",but the drsosc runs well . when I connect to other win7*64bits computer,only one of them runs property! Is there any driver else |