 Tue Apr 11 09:07:33 2017, Giovanni Bruni, drs4 registers behaviour
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Thank you Stefan for replying!
I have still the RESET issue in mind: how would you suggest to reset properly the DRS? Is there a particular procedure to follow instead of just
sending a negative pulse to the RESET pin? Is it preferable to turn the DRS off and then restart? |
 Thu Jun 18 17:33:05 2015, Gregor Kramberger, drs 5.03 and windows 8.1
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I have problems with driver installation on windows 8.1 (software version 5.03). I have sen that that has been an issue before (driver signing)
and I would like to know if this has been solved. We run several DRS4 evaluation boards on different PCs all running Win7 without any problems.
Therefore we are almost confident that it is related to Win 8.1. Thanks. |
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Fri Jun 19 12:32:10 2015, Gregor Kramberger, drs 5.03 and windows 8.1
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Gregor Kramberger wrote:
I have problems with driver |
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Fri Jan 13 12:58:22 2017, Gregor Kramberger, DRS software doesn't work under Windows XP SP3
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Hi all
I have a problem with running the DRSOSC under windows XP SP3. We have some hardware which is not supported under newer versions of windows and
we would like to use DRS boards along it, therefore we would higly appreciated any help in that direction. We have installed the software (V 5.03) to two |
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Wed Sep 7 16:45:17 2011, Guillaume Blanchard, DRS4 and AD9222
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Normal
0
21
false
false
false
MicrosoftInternetExplorer4
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Fri Sep 9 09:28:57 2011, Guillaume Blanchard, DRS4 and AD9222
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Thank you for your answers,
Another question : Have you ever tried to split the differential signal at the output of the DRS4 chip ? For
example to feed both an AD9222 and a diff. amplifier (followed by discriminators) ? |
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Mon Apr 23 10:38:51 2012, Guillaume Blanchard, DRS4 Initialization
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Hello,
I am writing a VHDL code to drive a DRS4 chip.
In order to configure the DRS4 chip, I have to set the "Config Register" and the "Write Shift Register" then ... (I do not |
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Wed Nov 21 08:34:52 2012, Gyuhee Kim, Question for using Multi board
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Hi.
I have 2 DRS4 evaluation V4 boards, and I want to use these 2 board to multi board DAQ system for 4 ch vs 4 ch DAQ. |
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Wed Nov 21 08:48:00 2012, Gyuhee Kim, Question for using Multi board
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Stefan Ritt wrote:
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Mon Dec 3 08:32:28 2012, Gyuhee Kim, Another question about using multi boards.
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Hi.
I asked about using multi boards some days ago, and I got answer to use external trigger. (Thanks Stefan!) |
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Mon Dec 3 11:40:35 2012, Gyuhee Kim, Another question about using multi boards.
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Stefan Ritt wrote:
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Wed Sep 7 17:28:25 2011, Hannes Friederich, DRS4 and AD9222
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Guillaume Blanchard wrote:
Normal
0
21
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Mon Sep 15 16:24:41 2014, Hannes Wachter, Timing Calibration Fail
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Hi,
has anyone experienced a shutdown of the DRSosc.exe or DRScl.exe when executing a Timing Calibration? Also, when we add the command b->CalibrateTiming(NULL);
to the drs_exam.cpp and run the exe, our program shuts down immediately and windows shows an error message (identical to DRSosc and DRScl). |
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Sat Feb 2 00:13:12 2019, Hans Steiger, Saving Rate (only 15Acq/s)
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Dear All,
when I use my Evaluation Board with some PMTs I can digitize 450 Acq/s or so. But when I want to save the waveforms the rate goes down. The Acqu. |
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Mon Feb 4 16:42:08 2019, Hans Steiger, Different Distances between the sampling points
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Dear All,
with the older software for my V5 Board i did not have the problem, that the distance between the sampling points (in time) is not the same (e.g.
a sampling point all 200ps for 5GS/s). |
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Mon Feb 4 17:36:49 2019, Hans Steiger, Different Distances between the sampling points
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Sorry.... but is there a solution or a Root Macro, that reads the waveforms into a Root-Tree? I simply can not work anymore with the data.
Can you tell me, which software was in use in early 2017?
All the best, |
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Sat Aug 29 22:00:30 2020, Hans Steiger, Dynamic Range Evaluation Board and Software
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Dear Evaluation Board Team,
currently I am facing the problem of digitizing pulses with an amplitude of -0.6V to -0.8V. As the dynamic range of the board is 1Vpp, this should |
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Mon Aug 31 16:44:12 2020, Hans Steiger, Channel Cascading
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Dear All,
I have a board with Channel Cascading Option. I have the problem, that it seems to be impossible to run all 4 Channels simultaneously for digitizing
pulses. I can just run even or odd channels but not even and odd ones? If I run in combined option, My question: If a board comes with this combined option, |
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Sun Jan 31 23:52:15 2010, Hao Huan, Failure In Flashing Xilinx PROM
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Hi Stefan,
I have an old-version DRS4 evaluation board which doesn't have the latest firmware. I tried to flash the drs_eval1.ipf boundary
scan chain into the XCF02S PROM with Xilinx IMPACT, and the firmware seemed to go through into the PROM. However, when I started the DRS command line interface |
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Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4
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Hi Stefan,
in the latest DRS4 datasheet I only saw your data of the DRS4 PLL locking time for 6GSPS sampling speed, with other rows "TBD".
Have you tried those lower frequencies? According to the datasheet I think the PLLLCK should be stabily low when the PLL is locked; am I right? However |