 Tue May 21 18:13:08 2024, Rebecca Hicks, Error when running drsosc
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Hi, I'm a student trying to figure out the DRS4 board. I cloned the github repo, but when I run drsosc, I get an error: Gtk-Message: 10:06:38.376:
Failed to load module "canberra-gtk-module". I'm not sure what that means. The oscilloscope window does open up for me though. Thanks for
any help! |
 Fri Jun 28 23:33:51 2024, Patricia Lecomti, Error when running drsosc
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Salut !
Je vois que tu rencontres un petit problème avec ton installation. Le message "Gtk-Message: Failed to load module 'canberra-gtk-module'"
indique que ton système essaie de charger un module GTK spécifique qui n'est pas installé. Heureusement, ce n'est pas un problème |
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Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing
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Using a test pulse split into two channels of the DRS4 Evaluation Board v5, I looked at the time resolution using a leading edge threshold.
The voltage and timing calibration was performed. One method (1) is to linearly interpolate between two points of the raw waveform that
is above and below the threshold (this is exactly the algorithm given in read_binary.c in the drs4 source distribution); and another (2) is to |
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Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing
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Just a follow-up update.
It turns out that I was using a cubic spline interpolation with smoothing. If I required the cubic spline to go through the sampled points, then
I obtained similar time resolution as the simple linear interpolation. |
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Thu Dec 6 09:23:36 2012, Martin Petriska, EVM rev4 board trigger change and drs_example
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I switched from rev 3 to rev 4 board, but have some problems with triggering, board is now waiting for trigger (rev.3 is working). How to do in
drs_exam.cpp for example triggering on Ch0 && CH1 ?
Software 4.0.0, windows version. |
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Fri Dec 14 21:49:29 2012, Stefan Ritt, EVM rev4 board trigger change and drs_example
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Martin Petriska wrote:
I switched from rev 3 to rev 4 board, but have some problems with triggering, board is now waiting |
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Sat Aug 29 22:00:30 2020, Hans Steiger, Dynamic Range Evaluation Board and Software
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Dear Evaluation Board Team,
currently I am facing the problem of digitizing pulses with an amplitude of -0.6V to -0.8V. As the dynamic range of the board is 1Vpp, this should |
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Mon Aug 31 10:52:42 2020, Stefan Ritt, Dynamic Range Evaluation Board and Software
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You cannot go below -0.5V for the inputs, since the board does not have an internal negative power supply, which would be necessary for that. If you
have -0.8V pulses, the easiest is to use a passive inverter at the input to convert it to a 0.8V pulse.
Stefan |
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Wed Dec 23 15:38:14 2015, mony orbach, Dtap stops toggling after 40msec
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Hi
the drs4 start to generate Dtap signal after reset and standard configuration.
while in reset Denable and Dwrite are low |
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Wed Dec 23 15:48:42 2015, Stefan Ritt, Dtap stops toggling after 40msec
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No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?
mony
orbach wrote:
Hi |
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Thu Dec 24 10:51:31 2015, mony orbach, Dtap stops toggling after 40msec
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my refclk is 1.25Mhz
what are the inputs and voltage you need to see?
Avdd and Dvdd are 2.5v |
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Thu Dec 24 12:45:41 2015, Stefan Ritt, Dtap stops toggling after 40msec
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I want to see the trace on the scope for the DTAP, the REFCLK, the DENABLE and the DWRITE.
Probably (but it's just a guess), you have a problem with the soldering of the DRS chip, maybe to the PLL loop filter. Or you chose the wrong
capacitor/resistor combination for the loop filter. There are ~10 other groupsl who did the same and it works for all of them, so there must be a problem |
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Sun Dec 27 15:06:59 2015, mony orbach, Dtap stops toggling after 40msec
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Hi
We have some meesurs to show (attached)
Dtap and Denable
Dtap+Denable in zoom
Dtap + Ref+
Dtap + Dspeed
From the screen shots |
Sun Dec 27 15:41:32 2015, mony orbach, Dtap stops toggling after 40msec 
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Hi
We have some measures to show (attached)
Dtap and Denable
Dtap+Denable in zoom
Dtap + Refck+
Dtap + Dspeed
From the screen |
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Mon Dec 28 11:05:15 2015, Stefan Ritt, Dtap stops toggling after 40msec
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Thanks for posting the plots. It really looks like the PLL is not working. I see two possible reasons: 1) The PLLEN bit in the configuration register
is not set and 2) The REFCLK signal does not reach the chip. We had cases whrere people had a hard time to solder the DRS4 correctly due to the small pins.
So if the REFCLK+ and REFCLK- signals have a poor connection, then the PLL of course won't work. Putting some more tin at the pins manually usually |
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Mon Dec 28 11:21:54 2015, mony orbach, Dtap stops toggling after 40msec
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Hi Stefan
Thanks for your input.
We are in the process of assemble another PCB board. |
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Wed Dec 30 16:25:35 2015, mony orbach, Dtap stops toggling after 40msec
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Hi
We have resolve the problem, the Dtap is now working correctly.
There were two problems: |
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Wed Dec 30 17:00:00 2015, Stefan Ritt, Dtap stops toggling after 40msec
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While I can understand 1., I'm puzzeled by 2.
If you put the chip in standby mode, the internal current sources are switched off, which of course make the domino wave non-functional. This
is clearly stated in the data sheet. |
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Thu Jan 14 14:00:26 2016, mony orbach, Dtap stops toggling after 40msec
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surrey i forgot to update..
after carefully examining our VHDL we found out that there are brief times that we put A0-A3 in 1111
after making shore that a0-a3 never get 1111 value thae drs4 woks as expected. |
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Thu Jan 14 14:11:06 2016, Stefan Ritt, Dtap stops toggling after 40msec
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Thanks for the update, I will add a note into the data sheet.
mony
orbach wrote:
surrey i forgot to update.. |