Thanks! After adding pull-down resistors the voltages come back to normal.

However there is another weird problem that arises: a reset pulse seems unable to set the internal shift registers to default values. For example, after reset without addressing the Config Register the PLL will not try to lock with external reference clock. Even if I explicitly address the Config Register after reset and have the PLL locked, some channels of the chip will give null output during readout while other channels work normally. Could it be that some channels are not initiated properly with the Domino circuit?

 Yes; I used RSRLOAD to trigger readout of all channels in parallel so the asymmetry between channels of the same chip is really a big puzzle. Also during reset DSPEED indeed goes to 2.5V, but after reset the PLL will not try to lock with the external reference clock and lower DSPEED. Instead the Domino circuit just oscillates at the highest frequency by itself.

A more confusing discovery is that the SRIN level before starting the Domino wave could affect the behavior of the PLL. I mean the level of SRIN when the chip is at A="1111" or "1010". Is SRIN supposed to influence the chip even in these standby or transparent modes?

Hi Stefan,

    I read in the DRS datasheet that the bandwidth for the transparent mode OUT+ is only 200MHz which I think cannot be improved by any active input buffer; so if you want to operate the chip for really high frequency input, would it be better to feed on-board discriminators not from the output of DRS but from the input end?

    Thanks!

Dear Dr. Ritt,

    In the DRS 4 datasheet it is recommended to sample the analog output of the chip after 8~10 ns of the SRCLK edge for it to stablize and thus a phase shift between SRCLK and the ADC sampling clock is necessary. However in the latest version of the evaluation board firmware the phase-shifted clock was generated but not really used for the ADC interface. Is there any reason for that?

Hi Stefan,

    I have a question regarding the DRS 4 evaluation board firmware for the 8051 controller embedded in the CY7C68013 USB chip: on the board the controller is running at 12 MHz and the FIFO interface of the USB chip is running at 30 MHz, so the number of delay cycles for synchronization as defined in fx2sdly.h should be (3*12000+5*30000-1)/(2*30000)=3, but the actual number used in drs_eval.c is (3*12000+5*48000-1)/(2*48000)=2, so there is a mismatch between the IFCLK frequency used in this calculation and the actual IFCLK frequency configured. Am I misunderstanding something or is there an explanation for that?

    Thanks,

Hao Huan

Dear All,

when I use my Evaluation Board with some PMTs I can digitize 450 Acq/s or so. But when I want to save the waveforms the rate goes down. The Acqu. rate with saving is in the range of 14Hz up to 24 Hz.

I normally use the .txt file. I try to use the 5GS/s but also with much lower sampling rate the saving rate is not getting much better. 

Is this a problem of my McBook connected to the Evaluation Board?

All the best,

Hans 

Dear All,

with the older software for my V5 Board i did not have the problem, that the distance between the sampling points (in time) is not the same (e.g. a sampling point all 200ps for 5GS/s). 

How can i fix this?

Can someone provide me the software for the board which is old enough to not have this problem. All my Root interpreters produce problems with this new data format.  Which version would be old enough?

All the best and thanks a lot,

Hans

Sorry.... but is there a solution or a Root Macro, that reads the waveforms into a Root-Tree? I simply can not work anymore with the data. 

Can you tell me, which software was in use in early 2017?

All the best,

Hans

Dear Evaluation Board Team,

currently I am facing the problem of digitizing pulses with an amplitude of -0.6V to -0.8V. As the dynamic range of the board is 1Vpp, this should be feasible. However, I do not know how to set in the software a correct range. I see only -0.5V/0.5V, and the two positive options. Normally I would use -0.5V/0.5V and give the thing an offset of 0.4V or so? Is this possible? Where can I set such a offset?

All the best,

Hans

Dear All,

I have a board with Channel Cascading Option. I have the problem, that it seems to be impossible to run all 4 Channels simultaneously for digitizing pulses. I can just run even or odd channels but not even and odd ones? If I run in combined option, My question: If a board comes with this combined option, is it still usable as a 4Ch Digitizer but with 1024bin traces?

All the best,

Hans

Hi,

has anyone experienced a shutdown of the DRSosc.exe or DRScl.exe when executing a Timing Calibration? Also, when we add the command b->CalibrateTiming(NULL); to the drs_exam.cpp and run the exe, our program shuts down immediately and windows shows an error message (identical to DRSosc and DRScl).

Any help is appreciated.

 Like Stefan pointed out, your time constraints are quite tight. In those 81 ns, you also need to deserialize the AD9222 output. Unless you implement some really fancy input comparison logic, this will consume another 1-2 ADC clock cycles. Perhaps you should first verify that your FPGA design actually can do its job within those 81 ns. In our system, we sample at only 1-2 GHz and have enough margin to implement really complex triggers in FPGA. But the total latency (ADC + FPGA deserialization) takes 250 ns.

Depending on the application, you do need a low-pass filter. Not only because of the noise, but also in order to be able to trigger reliably. Using fast PMTs for example, you will not be able to see all pulses in full size if the bandwidth is 50 MHz and you're only sampling at 65 MSPS.

Hannes

 Hi.

I have 2 DRS4 evaluation V4 boards, and I want to use these 2 board to multi board DAQ system for 4 ch vs 4 ch DAQ.

But there is no option for multi board use. I just only find the multi board trigger mode check button on DRS4 Oscilloscope program, but I couldn`t check. 

Is there any method to use multi board?

Best regards.

Gyuhee.

 Thanks Stefan.

I will build external trigger system. 

 Hi.

I asked about using multi boards some days ago, and I got answer to use external trigger. (Thanks Stefan!)

And here is another question. I made two external triggers and try to acquire coincidence data using two boards. but DRS Oscilloscope program can connect only one board and don`t acquire both of them simultaneously.

So I tried to use two computer for each board separately, but, well, you already know, I failed to acquire because two computers don`t promise to synchronize the two boards acquisition.

Is there any method to solve this problem?

1. I want to acquire coincidence data from the two DRS 4 Evaluation board V4 simultaneosly.

2. I have external trigger to provide the two boards at the same time.

3. How can I get data from the two boards?

Best regards.

Gyuhee.

That`s very bad news for me. I don`t have much time to study & write C programming...

Anyway, Thank you very much Stefan.

Best regards.

Gyuhee.

Hello,

I am designing a DAQ board with both DRS4 + AD9222 and a  FPGA to monitor.

Do I have to change the default value of O-OFS ?

Does a simple low-pass filter (series resistor + capacitor) on each AD9222 input is enough to limit the noise ?

I am planning to use the (DRS4,AD9222,FPGA) group as both a trigger and digitizing system (as shown in the DRS4 datasheet). The DRS4 will be working at 5Ghz with 8 active channels.
So each channel will have a time depth of 1/5Ghz x 1024 = 204.8ns. So, in order to miss nothing, the ADC latency + the trigger decision must be inferior to 204.8ns, am I correct ?
This leads me to implement on my board the 65Mhz version of the AD9222 as this converter has a 8 clock period latency, i.e. 123ns and it left me 81ns to perform a trigger decision ?

Cordially,

G.Blanchard

Thank you for your answers,

Another question : Have you ever tried to split the differential signal at the output of the DRS4 chip ? For example to feed both an AD9222 and a diff. amplifier (followed by discriminators) ?

Hello,

I am writing a VHDL code to drive a DRS4 chip.

In order to configure the DRS4 chip, I have to set the "Config Register" and the "Write Shift Register" then ... (I do not plan to use simultaneous WR and R so I guess the Write Config Reg. is not needed)

My question is :

When do we have to perform a "Read Shift Register Initialization" ?

Every time before a full read-out, or juste once after a DRS4 reset ?

Further more, is this initialization needed for the ROI mode ?

And at last do the level of the DENABLE and DWRITE signals matter for the "Read Shift Register Initialization" ?

(To sum up : what is the purpose of the Read Shift Register and how does it work ?)

Cordially,

G.Blanchard.

I have problems with driver installation on windows 8.1 (software version 5.03). I have sen that that has been an issue before (driver signing) and I would like to know if this has been solved. We run several DRS4 evaluation boards on different PCs all running Win7 without any problems. Therefore we are almost confident that it is related to Win 8.1. Thanks.