| ID |
Date |
Author |
Subject |
|
27
|
Tue Dec 22 01:30:55 2009 |
Jinhong Wang | Trigger of DRS4 |
| Stefan Ritt wrote: |
|
| Jinhong Wang wrote: |
|
| Stefan Ritt wrote: |
|
| Jinhong Wang wrote: |
|
Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation of trigger signal to stop DRS4 sampling process for readout of sampled waveform.
As metioned in the datasheet of DRS4, the chip samples the analog input every domino sampling period. After finished sampling a waveform, the sampling process can be stoped by lowering the DWRITE while keeping DENABLE high. But the analog input is asychronous to the Domino CLK. Then, how can we know when to stop the domino sampling process to read out the sampled waveform? Of course, a trigger can be used. But from my present knowledge of DRS4, trigger can only be generated from analog input. Analog input is splited into two channels, one to DRS4 analog input, the other to FPGA as the trigger. However, splitting analog inputs increases the system design complexity, and may lower the total performace. So what is your suggestion?
In our system, there are 8 analog inputs to a signal DRS4 chip, the outputs of DRS4 chip are connected to an 8-channel 14 bit ADC ( AD9252). It wold be kind of you to inform me about the most applicable approach for readout of DRS4 sampled wavefrom.
Best regards.
Sincerely,
Jinhong Wang (wangjinh@mail.ustc.edu.cn)
|
Indeed you have to make an external trigger. The evaluation board uses the "transparent mode" of the DRS4 to "mirror" the input signal at the output, then puts a comparator there. The schematics of the evaluation board is in the manual. This does then not degrate the analog performance. You can of course also split the signal at the input, this will only add a minor additional load to the input signal, since the load of the DRS4 chips itself is much bigger than that of any comparator.
An alternative is to turn on the transparent mode and continuously digitize all 8 outputs with your AD9252. Then you make the trigger purely digital in your FPGA. You can put there a comparator, or even more complex logic like multiplicity etc. Note however that this causes some latency, since the ADC has a pipeline which is quite long, so you have to buffer the latency of your trigger in the analog window of the DRS4 sampling cells. Like if you run the DRS4 at 1 GSPS, you can accomodate 1024 ns of sampling depth, which is good for maybe 500 ns of trigger latency plus 500 ns of the waveform of interest.
|
Thank you. The transparent mode can be really helpful. Can you provide me in more details of the chip's transparent mode? I am still confused about the following aspects.
I notice that DRS4 samples the analog wave in the way "clear before write", and in the transparent mode, there will be certain delay before the trigger logic stops the sampling process. So,does it mean that the waveform recording process per Domino sampling cycle will not degrade the amplitude of the analog signal? Hence, for two idential analog inputs, one with a trigger latency of 500 ns and the other of 510 ns, the sampled waveform is identical, what differs is the starting number of the first active sampling cell, where the reading process considered to be started. Is that right? Looking forward to your insight.
Best regrads.
Sincerely,
Jinhong Wang (wangjinh@mail.ustc.edu.cn)
|
The amplitude of the analog signal is not degraded by the transparent mode, since the signal is buffered on the chip, and the output of this buffer is send off the chip. The waveform digitizing of course requires quite some current to charge up all capacitors, so there is maximum current of ~1mA for 5 GSPS. If you only have a weak signal source, your bandwidth might be limited by that. On the evaluation board for example we use passive transformers to produce the differential input signal from a single-ended signal. Although the transformers are rated 1 GHz Bandwidth, we only achieve 200 MHz with the passive transformers. By using active high speed differential drivers, you can get about 700 MHz right now.
If you have two channels with 500 ns and 510 ns trigger latency, there is no difference in the "domino stop position" since there is only one domino circuit per chip which can be stopped. So the stop position is the same for all eight channels on a chip.
|
So you mean there is an analog buffer per channel? The analog signal is buffered there, before entering the sampling cells? Then, when will the buffer content be released and cleared? How shall I handle "Dwite" and "Denable" during a complete operation when an analog signal arrives in the transparent mode? I cannot find more information beyond the datasheet, a detailed description of the transparent mode (and the analog buffer, if possible) will be really helpful for me.
Best,
Sincerely,
Jinhong Wang (wangjinh@mail.ustc.edu.cn) |
|
26
|
Mon Dec 21 16:52:08 2009 |
Stefan Ritt | Trigger of DRS4 |
| Jinhong Wang wrote: |
|
| Stefan Ritt wrote: |
|
| Jinhong Wang wrote: |
|
Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation of trigger signal to stop DRS4 sampling process for readout of sampled waveform.
As metioned in the datasheet of DRS4, the chip samples the analog input every domino sampling period. After finished sampling a waveform, the sampling process can be stoped by lowering the DWRITE while keeping DENABLE high. But the analog input is asychronous to the Domino CLK. Then, how can we know when to stop the domino sampling process to read out the sampled waveform? Of course, a trigger can be used. But from my present knowledge of DRS4, trigger can only be generated from analog input. Analog input is splited into two channels, one to DRS4 analog input, the other to FPGA as the trigger. However, splitting analog inputs increases the system design complexity, and may lower the total performace. So what is your suggestion?
In our system, there are 8 analog inputs to a signal DRS4 chip, the outputs of DRS4 chip are connected to an 8-channel 14 bit ADC ( AD9252). It wold be kind of you to inform me about the most applicable approach for readout of DRS4 sampled wavefrom.
Best regards.
Sincerely,
Jinhong Wang (wangjinh@mail.ustc.edu.cn)
|
Indeed you have to make an external trigger. The evaluation board uses the "transparent mode" of the DRS4 to "mirror" the input signal at the output, then puts a comparator there. The schematics of the evaluation board is in the manual. This does then not degrate the analog performance. You can of course also split the signal at the input, this will only add a minor additional load to the input signal, since the load of the DRS4 chips itself is much bigger than that of any comparator.
An alternative is to turn on the transparent mode and continuously digitize all 8 outputs with your AD9252. Then you make the trigger purely digital in your FPGA. You can put there a comparator, or even more complex logic like multiplicity etc. Note however that this causes some latency, since the ADC has a pipeline which is quite long, so you have to buffer the latency of your trigger in the analog window of the DRS4 sampling cells. Like if you run the DRS4 at 1 GSPS, you can accomodate 1024 ns of sampling depth, which is good for maybe 500 ns of trigger latency plus 500 ns of the waveform of interest.
|
Thank you. The transparent mode can be really helpful. Can you provide me in more details of the chip's transparent mode? I am still confused about the following aspects.
I notice that DRS4 samples the analog wave in the way "clear before write", and in the transparent mode, there will be certain delay before the trigger logic stops the sampling process. So,does it mean that the waveform recording process per Domino sampling cycle will not degrade the amplitude of the analog signal? Hence, for two idential analog inputs, one with a trigger latency of 500 ns and the other of 510 ns, the sampled waveform is identical, what differs is the starting number of the first active sampling cell, where the reading process considered to be started. Is that right? Looking forward to your insight.
Best regrads.
Sincerely,
Jinhong Wang (wangjinh@mail.ustc.edu.cn)
|
The amplitude of the analog signal is not degraded by the transparent mode, since the signal is buffered on the chip, and the output of this buffer is send off the chip. The waveform digitizing of course requires quite some current to charge up all capacitors, so there is maximum current of ~1mA for 5 GSPS. If you only have a weak signal source, your bandwidth might be limited by that. On the evaluation board for example we use passive transformers to produce the differential input signal from a single-ended signal. Although the transformers are rated 1 GHz Bandwidth, we only achieve 200 MHz with the passive transformers. By using active high speed differential drivers, you can get about 700 MHz right now.
If you have two channels with 500 ns and 510 ns trigger latency, there is no difference in the "domino stop position" since there is only one domino circuit per chip which can be stopped. So the stop position is the same for all eight channels on a chip. |
|
25
|
Mon Dec 21 10:17:05 2009 |
Jinhong Wang | Trigger of DRS4 |
| Stefan Ritt wrote: |
|
| Jinhong Wang wrote: |
|
Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation of trigger signal to stop DRS4 sampling process for readout of sampled waveform.
As metioned in the datasheet of DRS4, the chip samples the analog input every domino sampling period. After finished sampling a waveform, the sampling process can be stoped by lowering the DWRITE while keeping DENABLE high. But the analog input is asychronous to the Domino CLK. Then, how can we know when to stop the domino sampling process to read out the sampled waveform? Of course, a trigger can be used. But from my present knowledge of DRS4, trigger can only be generated from analog input. Analog input is splited into two channels, one to DRS4 analog input, the other to FPGA as the trigger. However, splitting analog inputs increases the system design complexity, and may lower the total performace. So what is your suggestion?
In our system, there are 8 analog inputs to a signal DRS4 chip, the outputs of DRS4 chip are connected to an 8-channel 14 bit ADC ( AD9252). It wold be kind of you to inform me about the most applicable approach for readout of DRS4 sampled wavefrom.
Best regards.
Sincerely,
Jinhong Wang (wangjinh@mail.ustc.edu.cn)
|
Indeed you have to make an external trigger. The evaluation board uses the "transparent mode" of the DRS4 to "mirror" the input signal at the output, then puts a comparator there. The schematics of the evaluation board is in the manual. This does then not degrate the analog performance. You can of course also split the signal at the input, this will only add a minor additional load to the input signal, since the load of the DRS4 chips itself is much bigger than that of any comparator.
An alternative is to turn on the transparent mode and continuously digitize all 8 outputs with your AD9252. Then you make the trigger purely digital in your FPGA. You can put there a comparator, or even more complex logic like multiplicity etc. Note however that this causes some latency, since the ADC has a pipeline which is quite long, so you have to buffer the latency of your trigger in the analog window of the DRS4 sampling cells. Like if you run the DRS4 at 1 GSPS, you can accomodate 1024 ns of sampling depth, which is good for maybe 500 ns of trigger latency plus 500 ns of the waveform of interest.
|
Thank you. The transparent mode can be really helpful. Can you provide me in more details of the chip's transparent mode? I am still confused about the following aspects.
I notice that DRS4 samples the analog wave in the way "clear before write", and in the transparent mode, there will be certain delay before the trigger logic stops the sampling process. So,does it mean that the waveform recording process per Domino sampling cycle will not degrade the amplitude of the analog signal? Hence, for two idential analog inputs, one with a trigger latency of 500 ns and the other of 510 ns, the sampled waveform is identical, what differs is the starting number of the first active sampling cell, where the reading process considered to be started. Is that right? Looking forward to your insight.
Best regrads.
Sincerely,
Jinhong Wang (wangjinh@mail.ustc.edu.cn) |
|
24
|
Tue Dec 15 14:38:09 2009 |
Stefan Ritt | Trigger of DRS4 |
| Jinhong Wang wrote: |
|
Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation of trigger signal to stop DRS4 sampling process for readout of sampled waveform.
As metioned in the datasheet of DRS4, the chip samples the analog input every domino sampling period. After finished sampling a waveform, the sampling process can be stoped by lowering the DWRITE while keeping DENABLE high. But the analog input is asychronous to the Domino CLK. Then, how can we know when to stop the domino sampling process to read out the sampled waveform? Of course, a trigger can be used. But from my present knowledge of DRS4, trigger can only be generated from analog input. Analog input is splited into two channels, one to DRS4 analog input, the other to FPGA as the trigger. However, splitting analog inputs increases the system design complexity, and may lower the total performace. So what is your suggestion?
In our system, there are 8 analog inputs to a signal DRS4 chip, the outputs of DRS4 chip are connected to an 8-channel 14 bit ADC ( AD9252). It wold be kind of you to inform me about the most applicable approach for readout of DRS4 sampled wavefrom.
Best regards.
Sincerely,
Jinhong Wang (wangjinh@mail.ustc.edu.cn)
|
Indeed you have to make an external trigger. The evaluation board uses the "transparent mode" of the DRS4 to "mirror" the input signal at the output, then puts a comparator there. The schematics of the evaluation board is in the manual. This does then not degrate the analog performance. You can of course also split the signal at the input, this will only add a minor additional load to the input signal, since the load of the DRS4 chips itself is much bigger than that of any comparator.
An alternative is to turn on the transparent mode and continuously digitize all 8 outputs with your AD9252. Then you make the trigger purely digital in your FPGA. You can put there a comparator, or even more complex logic like multiplicity etc. Note however that this causes some latency, since the ADC has a pipeline which is quite long, so you have to buffer the latency of your trigger in the analog window of the DRS4 sampling cells. Like if you run the DRS4 at 1 GSPS, you can accomodate 1024 ns of sampling depth, which is good for maybe 500 ns of trigger latency plus 500 ns of the waveform of interest. |
|
23
|
Mon Dec 14 10:14:16 2009 |
Jinhong Wang | Trigger of DRS4 | Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation of trigger signal to stop DRS4 sampling process for readout of sampled waveform.
As metioned in the datasheet of DRS4, the chip samples the analog input every domino sampling period. After finished sampling a waveform, the sampling process can be stoped by lowering the DWRITE while keeping DENABLE high. But the analog input is asychronous to the Domino CLK. Then, how can we know when to stop the domino sampling process to read out the sampled waveform? Of course, a trigger can be used. But from my present knowledge of DRS4, trigger can only be generated from analog input. Analog input is splited into two channels, one to DRS4 analog input, the other to FPGA as the trigger. However, splitting analog inputs increases the system design complexity, and may lower the total performace. So what is your suggestion?
In our system, there are 8 analog inputs to a signal DRS4 chip, the outputs of DRS4 chip are connected to an 8-channel 14 bit ADC ( AD9252). It wold be kind of you to inform me about the most applicable approach for readout of DRS4 sampled wavefrom.
Best regards.
Sincerely,
Jinhong Wang (wangjinh@mail.ustc.edu.cn) |
|
22
|
Wed Nov 4 14:42:22 2009 |
Stefan Ritt | outline dimension of DRS4 |
| Jinhong Wang wrote: |
|
Fig.1 typical dimension of QFN package
Above is the typical dimension specification for QFN package. I cann't find the corresponding "T1" as in Fig.1 in the DRS4 documents, nor any of the tolerance of the dimensions, which are usually expressed in the form of a range between a min. value and a max. value.
So will you specify the dimension of "T1" and "W1", and the dimension tolerance of them?
Thanks and best wishes!
Jinhong Wang University of Science and Technology of China
|
Please find attached the complete dimensions. |
| Attachment 1: qfn76.png
|
|
|
21
|
Fri Oct 30 03:31:54 2009 |
Jinhong Wang | outline dimension of DRS4 |
Fig.1 typical dimension of QFN package
Above is the typical dimension specification for QFN package. I cann't find the corresponding "T1" as in Fig.1 in the DRS4 documents, nor any of the tolerance of the dimensions, which are usually expressed in the form of a range between a min. value and a max. value.
So will you specify the dimension of "T1" and "W1", and the dimension tolerance of them?
Thanks and best wishes!
Jinhong Wang University of Science and Technology of China |
|
20
|
Mon Oct 19 12:46:12 2009 |
Stefan Ritt | output common mode voltage of DRS4 |
| Jinhong Wang wrote: |
|
Does it mean that this buffer shifts a voltage of about 1.3V for the primary differential range?
|
No. It shifts about ROFS-0.25V. So only if ROFS=1.55V, the shift will be 1.3V.
| Jinhong Wang wrote: |
|
Again for the differential range of -0.5V~0.5V, can the common mode voltage of the analog output at OUT+/OUT- be chaned?
|
Just read the datasheet under "ANALOG OUTPUTS". I'm sorry if I did not describe this clearly, but the U+ voltage is fixed (only dependent on ROFS), and U- can be calculated using Uofs as written in the datasheet.
| Jinhong Wang wrote: |
|
In the example presented in the datasheet, OUT+ is 0.8V~1.8V and OUT- is 1.8V~0.8V. So for an output swing of 2V p-p, can the common mode voltage be modified to the desired value? Supposed that the input ranges from -0.5V~0.5V.
|
OUT+ is 0.8V~1.8V, OUT- is 2*Uofs-OUT+. So you can only change the OUT- level, not the OUT+ level. |
|
19
|
Mon Oct 19 11:26:29 2009 |
Jinhong Wang | output common mode voltage of DRS4 | Hello Mr. Stifan.Ritt
In the DSR4 datasheet, it is mentioned that there is an additional buffer at each analog output, this buffer shifts the the differential range of -0.5V~0.5V to 0.8V~1.8V. Does it mean that this buffer shifts a voltage of about 1.3V for the primary differential range?
Again for the differential range of -0.5V~0.5V, can the common mode voltage of the analog output at OUT+/OUT- be chaned? In the example presented in the datasheet, OUT+ is 0.8V~1.8V and OUT- is 1.8V~0.8V. So for an output swing of 2V p-p, can the common mode voltage be modified to the desired value? Supposed that the input ranges from -0.5V~0.5V.
Thank you!
Jinhong Wang |
|
18
|
Mon Oct 19 09:13:00 2009 |
Stefan Ritt | BIAS Pin of DRS4 |
| Jinhong Wang wrote: |
|
Dear Mr. Stefan Ritt.
Thank u for your timely response on "DSR4 Full Readout Mode", I received it from Professor Qi An, who is my PhD supervisor.
I am currently going through the DRS4 datasheet. Well, can you give some specification on the usage of "BIAS" pin of DRS4? It is just metioned in the datasheet as bias of internal buffer. What is the internal buffer exactly reffered to here? The MUXOUT buffer of channel 8 or else? Does it have some relationship to O_OFS? I mean, if the reference voltage to BIAS is changed, how will the output be influenced?
Looking forward to hearing from you soon.
Jinhong Wang
Fast Electronics LAB. of University of Science and Technology of China.
|
"internal buffers" are all internal operational amplifiers in the DRS4 chip. Every OPAMP needs a bias (just look it up in any electronics textbook), which determines the linearity and the speed of the OPAMP. When designing DRS4, I was not sure if the required BIAS voltage changes over time, or between chips, so I made it available at a pin, which is a common technique in chip design. But it turns out now that this voltage is not very critical, so just keeping the pin open will work in most cases. |
|
17
|
Mon Oct 19 09:06:43 2009 |
Jinhong Wang | BIAS Pin of DRS4 | Dear Mr. Stefan Ritt.
Thank u for your timely response on "DSR4 Full Readout Mode", I received it from Professor Qi An, who is my PhD supervisor.
I am currently going through the DRS4 datasheet. Well, can you give some specification on the usage of "BIAS" pin of DRS4? It is just metioned in the datasheet as bias of internal buffer. What is the internal buffer exactly reffered to here? The MUXOUT buffer of channel 8 or else? Does it have some relationship to O_OFS? I mean, if the reference voltage to BIAS is changed, how will the output be influenced?
Looking forward to hearing from you soon.
Jinhong Wang
Fast Electronics LAB. of University of Science and Technology of China. |
|
16
|
Fri Oct 16 10:16:10 2009 |
Stefan Ritt | DSR4 Full Readout Mode |
| Jinhong Wang wrote: |
|
Hello Mr. Stefan Ritt
In DSR4 DATASHEET Rev.0.8 Page13, I noticed you metioned the samping should occur after 38 ns after the rising edge of SRCLK when the multiplexer is used. So what is suggested value(delay time between sampling and the rising edge of SRCLK) for the parallel mode,in which the multiplexer is not used?
Best wishes!
Jinhong Wang
|
The clock-to-output delay is the same if one uses the multiplexer or not. I found however that in most cases the delay of 38 ns needs some fine tuning to get optimal performance. So I typically use a shifted clock generated by the FPGA clock manager with a programmable delay (+-5 ns for Xilinx) and optimize this in the running system. |
|
15
|
Fri Oct 16 09:51:03 2009 |
Jinhong Wang | DSR4 Full Readout Mode | Hello Mr. Stefan Ritt
In DSR4 DATASHEET Rev.0.8 Page13, I noticed you metioned the samping should occur after 38 ns after the rising edge of SRCLK when the multiplexer is used. So what is suggested value(delay time between sampling and the rising edge of SRCLK) for the parallel mode,in which the multiplexer is not used?
Best wishes!
Jinhong Wang |
|
14
|
Wed Oct 14 23:53:05 2009 |
Armin Kolb | DRS_exam using USB Evaluation Board with OS X | For the users using a Macintosh,
after several hours the Evaluation Board is working on my Macintosh (intel).
1) install the development package with xcode, its on the OS X installation DVD
2) install the libusb binary from http://www.ellert.se/twain-sane/
3) modify the makefile for compiling drs_exam (attached) afterwards it's running perfect!
best,
Armin
|
| Attachment 1: Makefile
|
########################################################
#
# Makefile for drs_exam executables
# under OS X Macintosh with Bash Shell
#
#
########################################################
CFLAGS = -g -O2 -Wall -Iinclude -DOS_LINUX -DHAVE_LIBUSB
LIBS = -lpthread -lutil -lusb
CPP_OBJ = DRS.o
OBJECTS = musbstd.o mxml.o strlcpy.o
all: drs_exam
drs_exam: $(OBJECTS) DRS.o drs_exam.o
$(CXX) $(CFLAGS) $(OBJECTS) DRS.o drs_exam.o -o drs_exam $(LIBS)
drs_exam.o: src/drs_exam.cpp include/mxml.h include/DRS.h
$(CXX) $(CFLAGS) -c $<
$(CPP_OBJ): %.o: src/%.cpp include/%.h include/mxml.h include/DRS.h
$(CXX) $(CFLAGS) $(WXFLAGS) -c $<
$(OBJECTS): %.o: src/%.c include/mxml.h include/DRS.h
$(CXX) $(CFLAGS) -c $<
clean:
rm -f *.o drscl drsosc
|
|
13
|
Wed Oct 7 17:58:20 2009 |
Stefan Ritt | VDD switch off speed | It turned out that the VDD switch off speed plays some important role. On our VME board, we have a linear regulator, then a 4.7 uF capacitor, then the DRS4 chip (DVDD and AVDD). When switching off the VME power, it takes quite some time to discharge the 4.7 uF capacitor, since the DRS4 chip goes into a high impedance mode if VDD < ~1V. This gives following VDD trace:
Rising edge is power on, falling edge is power off. Note the horizontal time scale of 2 s/div. So to get below 0.3 V or so, it takes up to 30 seconds. If the power is switched back on when AVDD is above 0.3V, the DRS4 chip can get into a weird state, where probably many domino waves are started and the chip draws an enormous amount of current. Typically the linear regulator limits the current, so the 2.5V drops to ~1.5V, and the board is not working. If people are aware of this and always wait >30sec. before turning the power on again, this is fine, but people might forget.
So the solution is to put a resistor (typically 100 Ohm to 1 kOhm) parallel to the 4.7 uF capacitor in order to have some resistive current load of a few mA. The discharge then looks like this:
Note the horizontal scale of 10ms/div. So after 30 ms AVDD is discharged and powering on the chip again does not do any harm. The same should be done to DVDD. |
|
12
|
Tue Oct 6 11:20:39 2009 |
Stefan Ritt | VDD instability | It has turned out that the stability of the AVDD and DVDD power supplies for the DRS4 are very critical. On the evaluation board I use a REG1117-2.5, on our VME board I use a ADP3338-2.5 for the DVDD power supply. When the domino wave is started, the power consumption of the DRS4 chip jumps up by ~40 mA, which has to be compensated by the linear regulator. Following screen shot shows what happens:
The blue trace is the DWRITE signal indicating the sampling phase when high. The yellow is the SRCLK showing when the readout takes place. The pink is now the DVDD power. It can be clearly seen that there is a dip of ~50 mV when the domino wave starts, a positive dip when it stops and another smaller dip when the readout starts. This causes strange effects: If the trigger arrives during the first dip, the actual sampling takes place when the DVDD is ~50 mV smaller, which leads to a baseline shift of a sampled 0V DC input voltage of about the same amount (-50 mV).
The obvious improvement is to put a huge capacitor on the power supply, but that does not help much:
The dip gets a bit smaller, but it's still there. So a better solution would be to use a faster LDO regulator. Please take care of this if you plan a new design.
Furthermore, I believe that the chip internally has some "warmup" phase, where the die heats up a bit when the additional 40 mA are drawn. So a "good" solution is to wait some time after starting the domino wave until one allows for triggers. Tests showed that a few milliseconds are necessary to keep the baseline shifts below a few millivolts. This of course decreases the dead time of the system significantly, so one has to choose the proper balance between increase dead time and increased base line shift. On some applications where a baseline shift is not an issue, one could opt for the minimum dead time. |
|
11
|
Thu Jul 9 09:11:03 2009 |
Stefan Ritt | Current problems with drs_exam.cpp | The current version of the DRS readout example program drs_exam.cpp has two problems:
- The sampling frequency cannot be changed, it will always stay in the region around 5 GSPS
- The waveform obtained by GetWave is rotated such that the first DRS cell corresponds to the first array bin
Both problems have been fixed and the fix will be contained in an upcoming software release. |
|
10
|
Tue Jul 7 16:39:57 2009 |
Stefan Ritt | Power up problem and remedy | Maybe some of you have experienced that the DRS4 chip can get pretty hot after power up. After it's initialized the first time, the power consumption goes back to normal. I finally found the cause of this problem and have a remedy. Here is the new paragraph from the updated data sheet:
During power-up, care has to be taken that the DENABLE and DWRITE signals are low. If not, the domino wave can get started before the power supply voltages are stable, which brings the DRS4 chip into a state where it draws a considerable amount of current and heats up significantly. This can be problematic if the signals are directly generated by a FPGA, since most FPGAs have internal pull-up resistors which get activated during the configuration phase of the FPGA. In such a case, the DENABLE and DWRITE signals should be connected to GND with a pull down resistor. This resistor should be much smaller than the FPGA pull-up resistor in order to keep the signals close to GND during the FPGA configuration. A typical value is 4.7 kOhm.
The attached schematics shows the location of the two required resistors. |
| Attachment 1: typical_mode.gif
|
|
|
9
|
Wed Jun 10 12:46:43 2009 |
Stefan Ritt | Input range switch added in Version 2.1.3 | A new software verison for the DRS4 Evaluation Board has been has been released. Version 2.1.3 adds a switch for the input range of the DRS4 board. Once can choose between -0.5V...0.5V and 0V...1V:
A board firmware update is not necessary for this. It was originally planned to have even a negative range -1V...0V, but this is not possible with the current board design. People who want to record negative pulses have to use an inverter to produce positive pulses. In a future version of the board it might be possible to include this functionality since this is determined by the analog front-end and not the DRS4 chip. |
|
8
|
Wed Apr 29 07:57:33 2009 |
Stefan Ritt | Simple example application to read a DRS evaluation board |
| Stefan Ritt wrote: |
|
Several people asked for s simple application to guide them in writing their own application to read out a DRS board. Such an application has been added in software revions 2.1.1 and is attached to this message. This example program drs_exam.cpp written in C++ does the following necessary steps to access a DRS board:
- Crate a "DRS" object and scan all USB devices
- Display found DRS boards
- Initialize the first found board and set the sampling frequency to 5 GSPS
- Enable internal trigger on channel #1 with 250 mV threshold
- Start acquisition and wait for a trigger
- Read two waveforms (both time and amplitude)
- Repeat this 10 times
I know that we are still missing a good documentation for the DRS API, but I have not yet found the time to do that. I hope the example program is enough for most people to start writing own programs. For Windows users (MS Visual C++ 8.0) there is a drs.sln project file, and for linux users there is a Makefile which can be used to compile this example program.
|
One note: The program drs_exam.cpp published in the previous message needs the current version of the DRS library in DRS.cpp and DRS.h. They are contained in the software release 2.1.1 which has to be downloaded. For simplicity, I attached the two files to this message. |
| Attachment 1: DRS.cpp
|
/********************************************************************
Name: DRS.cpp
Created by: Stefan Ritt, Matthias Schneebeli
Contents: Library functions for DRS mezzanine and USB boards
$Id: DRS.cpp 13351 2009-04-28 11:12:54Z ritt@PSI.CH $
\********************************************************************/
#include <stdio.h>
#include <math.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <algorithm>
#include <sys/stat.h>
#include "strlcpy.h"
#ifdef _MSC_VER
#pragma warning(disable:4996)
# include <windows.h>
# include <direct.h>
#else
# include <unistd.h>
# include <sys/time.h>
inline void Sleep(useconds_t x)
{
usleep(x * 1000);
}
#endif
#ifdef _MSC_VER
#include <conio.h>
#define drs_kbhit() kbhit()
#else
#include <sys/ioctl.h>
int drs_kbhit()
{
int n;
ioctl(0, FIONREAD, &n);
return (n > 0);
}
static inline int getch()
{
return getchar();
}
#endif
#include <DRS.h>
#ifdef _MSC_VER
extern "C" {
#endif
#include <mxml.h>
#ifdef _MSC_VER
}
#endif
/*---- minimal FPGA firmvare version required for this library -----*/
const int REQUIRED_FIRMWARE_VERSION_DRS2 = 5268;
const int REQUIRED_FIRMWARE_VERSION_DRS3 = 6981;
const int REQUIRED_FIRMWARE_VERSION_DRS4 = 13191;
/*---- VME addresses -----------------------------------------------*/
#ifdef HAVE_VME
/* assuming following DIP Switch settings:
SW1-1: 1 (off) use geographical addressing (1=left, 21=right)
SW1-2: 1 (off) \
SW1-3: 1 (off) > VME_WINSIZE = 8MB, subwindow = 1MB
SW1-4: 0 (on) /
SW1-5: 0 (on) reserverd
SW1-6: 0 (on) reserverd
SW1-7: 0 (on) reserverd
SW1-8: 0 (on) \
|
SW2-1: 0 (on) |
SW2-2: 0 (on) |
SW2-3: 0 (on) |
SW2-4: 0 (on) > VME_ADDR_OFFSET = 0
SW2-5: 0 (on) |
SW2-6: 0 (on) |
SW2-7: 0 (on) |
SW2-8: 0 (on) /
which gives
VME base address = SlotNo * VME_WINSIZE + VME_ADDR_OFFSET
= SlotNo * 0x80'0000
*/
#define GEVPC_BASE_ADDR 0x00000000
#define GEVPC_WINSIZE 0x800000
#define GEVPC_USER_FPGA (GEVPC_WINSIZE*2/8)
#define PMC1_OFFSET 0x00000
#define PMC2_OFFSET 0x80000
#define PMC_CTRL_OFFSET 0x00000 /* all registers 32 bit */
#define PMC_STATUS_OFFSET 0x10000
#define PMC_FIFO_OFFSET 0x20000
#define PMC_RAM_OFFSET 0x40000
#endif // HAVE_VME
/*---- USB addresses -----------------------------------------------*/
#define USB_TIMEOUT 1000 // one second
#ifdef HAVE_USB
#define USB_CTRL_OFFSET 0x00 /* all registers 32 bit */
#define USB_STATUS_OFFSET 0x40
#define USB_RAM_OFFSET 0x80
#define USB_CMD_IDENT 0 // Query identification
#define USB_CMD_ADDR 1 // Address cycle
#define USB_CMD_READ 2 // "VME" read <addr><size>
#define USB_CMD_WRITE 3 // "VME" write <addr><size>
#define USB_CMD_READ12 4 // 12-bit read <LSB><MSB>
#define USB_CMD_WRITE12 5 // 12-bit write <LSB><MSB>
#define USB2_CMD_READ 1
#define USB2_CMD_WRITE 2
#define USB2_CTRL_OFFSET 0x00000 /* all registers 32 bit */
#define USB2_STATUS_OFFSET 0x10000
#define USB2_FIFO_OFFSET 0x20000
#define USB2_RAM_OFFSET 0x40000
#endif // HAVE_USB
/*---- Register addresses ------------------------------------------*/
#ifndef T_CTRL
#define T_CTRL 1
#define T_STATUS 2
#define T_RAM 3
#define T_FIFO 4
#endif
#define REG_CTRL 0x00000 /* 32 bit control reg */
#define REG_DAC_OFS 0x00004
#define REG_DAC0 0x00004
#define REG_DAC1 0x00006
#define REG_DAC2 0x00008
#define REG_DAC3 0x0000A
#define REG_DAC4 0x0000C
#define REG_DAC5 0x0000E
#define REG_DAC6 0x00010
#define REG_DAC7 0x00012
#define REG_CHANNEL_CONFIG 0x00014 // low byte
#define REG_CONFIG 0x00014 // high byte
#define REG_CHANNEL_SPAN 0x00016
#define REG_FREQ_SET_HI 0x00018 // DRS2
#define REG_FREQ_SET_LO 0x0001A // DRS2
#define REG_TRG_DELAY 0x00018 // DRS4
#define REG_FREQ_SET 0x0001A // DRS4
#define REG_TRIG_DELAY 0x0001C
#define REG_LMK_MSB 0x0001C // DRS4 Mezz
#define REG_CALIB_TIMING 0x0001E // DRS2
#define REG_EEPROM_PAGE 0x0001E // DRS4
#define REG_LMK_LSB 0x0001E // DRS4 Mezz
#define REG_MAGIC 0x00000
#define REG_BOARD_TYPE 0x00002
#define REG_STATUS 0x00004
#define REG_RDAC_OFS 0x0000E
#define REG_RDAC0 0x00008
#define REG_STOP_CELL0 0x00008
#define REG_RDAC1 0x0000A
#define REG_STOP_CELL1 0x0000A
#define REG_RDAC2 0x0000C
#define REG_STOP_CELL2 0x0000C
#define REG_RDAC3 0x0000E
#define REG_STOP_CELL3 0x0000E
#define REG_RDAC4 0x00000
#define REG_RDAC5 0x00002
#define REG_RDAC6 0x00014
#define REG_RDAC7 0x00016
#define REG_EVENTS_IN_FIFO 0x00018
#define REG_EVENT_COUNT 0x0001A
#define REG_FREQ1 0x0001C
#define REG_FREQ2 0x0001E
#define REG_TEMPERATURE 0x00020
#define REG_TRIGGER_BUS 0x00022
#define REG_SERIAL_BOARD 0x00024
#define REG_VERSION_FW 0x00026
/*------------------------------------------------------------------*/
using namespace std;
#ifdef HAVE_USB
#define USB2_BUFFER_SIZE (1024*1024+10)
unsigned char static *usb2_buffer = NULL;
#endif
/*------------------------------------------------------------------*/
DRS::DRS()
: fNumberOfBoards(0)
#ifdef HAVE_VME
, fVmeInterface(0)
#endif
{
#ifdef HAVE_USB
MUSB_INTERFACE *usb_interface;
#endif
#if defined(HAVE_VME) || defined(HAVE_USB)
int index = 0, i = 0;
#endif
memset(fError, 0, sizeof(fError));
#ifdef HAVE_VME
unsigned short type, fw, magic, serial, temperature;
mvme_addr_t addr;
if (mvme_open(&fVmeInterface, 0) == MVME_SUCCESS) {
mvme_set_am(fVmeInterface, MVME_AM_A32);
mvme_set_dmode(fVmeInterface, MVME_DMODE_D16);
/* check all VME slave slots */
for (index = 2; index <= 21; index++) {
/* check PMC1 */
addr = GEVPC_BASE_ADDR + index * GEVPC_WINSIZE; // VME board base address
addr += GEVPC_USER_FPGA; // UsrFPGA base address
addr += PMC1_OFFSET; // PMC1 offset
mvme_set_dmode(fVmeInterface, MVME_DMODE_D16);
i = mvme_read(fVmeInterface, &magic, addr + PMC_STATUS_OFFSET + REG_MAGIC, 2);
if (i == 2) {
if (magic != 0xC0DE) {
printf("Found old firmware, please upgrade immediately!\n");
fBoard[fNumberOfBoards] = new DRSBoard(fVmeInterface, addr, (index - 2) << 1);
fNumberOfBoards++;
} else {
/* read board type */
mvme_read(fVmeInterface, &type, addr + PMC_STATUS_OFFSET + REG_BOARD_TYPE, 2);
type &= 0xFF;
if (type == 2 || type == 3 || type == 4) { // DRS2 or DRS3 or DRS4
/* read firmware number */
mvme_read(fVmeInterface, &fw, addr + PMC_STATUS_OFFSET + REG_VERSION_FW, 2);
/* read serial number */
mvme_read(fVmeInterface, &serial, addr + PMC_STATUS_OFFSET + REG_SERIAL_BOARD, 2);
/* read temperature register to see if CMC card is present */
mvme_read(fVmeInterface, &temperature, addr + PMC_STATUS_OFFSET + REG_TEMPERATURE, 2);
/* LED blinking */
#if 0
do {
data = 0x00040000;
mvme_write(fVmeInterface, addr + PMC_CTRL_OFFSET + REG_CTRL, &data, sizeof(data));
mvme_write(fVmeInterface, addr + PMC2_OFFSET + PMC_CTRL_OFFSET + REG_CTRL, &data,
sizeof(data));
Sleep(500);
data = 0x00000000;
mvme_write(fVmeInterface, addr + PMC_CTRL_OFFSET + REG_CTRL, &data, sizeof(data));
mvme_write(fVmeInterface, addr + PMC2_OFFSET + PMC_CTRL_OFFSET + REG_CTRL, data,
sizeof(data));
Sleep(500);
} while (1);
#endif
if (temperature == 0xFFFF) {
//printf("slot %d, fw %d, no CMC board in upper slot\n", index, fw);
} else {
//printf("slot %d, fw %d, CMC serial %d in upper slot\n", index, fw, serial);
fBoard[fNumberOfBoards] = new DRSBoard(fVmeInterface, addr, (index - 2) << 1);
if (fBoard[fNumberOfBoards]->HasCorrectFirmware())
fNumberOfBoards++;
else
sprintf(fError, "Wrong firmware version: board has %d, required is %d\n",
fBoard[fNumberOfBoards]->GetFirmwareVersion(),
fBoard[fNumberOfBoards]->GetRequiredFirmwareVersion());
}
}
}
}
/* check PMC2 */
addr = GEVPC_BASE_ADDR + index * GEVPC_WINSIZE; // VME board base address
addr += GEVPC_USER_FPGA; // UsrFPGA base address
addr += PMC2_OFFSET; // PMC2 offset
mvme_set_dmode(fVmeInterface, MVME_DMODE_D16);
i = mvme_read(fVmeInterface, &fw, addr + PMC_STATUS_OFFSET + REG_MAGIC, 2);
if (i == 2) {
if (magic != 0xC0DE) {
printf("Found old firmware, please upgrade immediately!\n");
fBoard[fNumberOfBoards] = new DRSBoard(fVmeInterface, addr, (index - 2) << 1 | 1);
fNumberOfBoards++;
} else {
... 5173 more lines ...
|
| Attachment 2: DRS.h
|
/********************************************************************
DRS.h, S.Ritt, M. Schneebeli - PSI
$Id: DRS.h 13347 2009-04-28 08:24:05Z ritt@PSI.CH $
********************************************************************/
#ifndef DRS_H
#define DRS_H
#include <stdio.h>
#include <string.h>
#ifdef HAVE_LIBUSB
# ifndef HAVE_USB
# define HAVE_USB
# endif
#endif
#ifdef HAVE_USB
# include <musbstd.h>
#endif // HAVE_USB
#ifdef HAVE_VME
# include <mvmestd.h>
#endif // HAVE_VME
/* disable "deprecated" warning */
#ifdef _MSC_VER
#pragma warning(disable: 4996)
#endif
#ifndef NULL
#define NULL 0
#endif
/* transport mode */
#define TR_VME 1
#define TR_USB 2
#define TR_USB2 3
/* address types */
#define T_CTRL 1
#define T_STATUS 2
#define T_RAM 3
#define T_FIFO 4
/* control register bit definitions */
#define BIT_START_TRIG (1<<0) // write a "1" to start domino wave
#define BIT_REINIT_TRIG (1<<1) // write a "1" to stop & reset DRS
#define BIT_SOFT_TRIG (1<<2) // write a "1" to stop and read data to RAM
#define BIT_EEPROM_WRITE_TRIG (1<<3) // write a "1" to write into serial EEPROM
#define BIT_EEPROM_READ_TRIG (1<<4) // write a "1" to read from serial EEPROM
#define BIT_AUTOSTART (1<<16)
#define BIT_DMODE (1<<17) // (*DRS2*) 0: single shot, 1: circular
#define BIT_LED (1<<18) // 1=on, 0=blink during readout
#define BIT_TCAL_EN (1<<19) // switch on (1) / off (0) for 33 MHz calib signal
#define BIT_TCAL_SOURCE (1<<20)
#define BIT_REFCLK_SOURCE (1<<20)
#define BIT_FREQ_AUTO_ADJ (1<<21) // DRS2/3
#define BIT_TRANSP_MODE (1<<21) // DRS4
#define BIT_ENABLE_TRIGGER1 (1<<22) // External LEMO/FP/TRBUS trigger
#define BIT_LONG_START_PULSE (1<<23) // (*DRS2*) 0:short start pulse (>0.8GHz), 1:long start pulse (<0.8GHz)
#define BIT_READOUT_MODE (1<<23) // (*DRS3*) 0:start from first bin, 1:start from domino stop
#define BIT_DELAYED_START (1<<24) // DRS2: start domino wave 400ns after soft trigger, used for waveform
// generator startup
#define BIT_NEG_TRIGGER (1<<24) // DRS4: use high-to-low trigger if set
#define BIT_ACAL_EN (1<<25) // connect DRS to inputs (0) or to DAC6 (1)
#define BIT_TRIGGER_DELAYED (1<<26) // select delayed trigger from trigger bus
#define BIT_DACTIVE (1<<27) // keep domino wave running during readout
#define BIT_STANDBY_MODE (1<<28) // put chip in standby mode
#define BIT_TR_SOURCE1 (1<<29) // trigger source selection bits
#define BIT_TR_SOURCE2 (1<<30) // trigger source selection bits
#define BIT_ENABLE_TRIGGER2 (1<<31) // analog threshold (internal) trigger
/* status register bit definitions */
#define BIT_RUNNING (1<<0) // one if domino wave running or readout in progress
#define BIT_NEW_FREQ1 (1<<1) // one if new frequency measurement available
#define BIT_NEW_FREQ2 (1<<2)
#define BIT_PLL_LOCKED0 (1<<1) // 1 if PLL has locked (DRS4 evaluation board only)
#define BIT_PLL_LOCKED1 (1<<2) // 1 if PLL DRS4 B has locked (DRS4 mezzanine board only)
#define BIT_PLL_LOCKED2 (1<<3) // 1 if PLL DRS4 C has locked (DRS4 mezzanine board only)
#define BIT_PLL_LOCKED3 (1<<4) // 1 if PLL DRS4 D has locked (DRS4 mezzanine board only)
#define BIT_EEPROM_BUSY (1<<5) // 1 if EEPROM operation in progress
/* configuration register bit definitions */
#define BIT_CONFIG_DMODE (1<<8) // 0: single shot, 1: circular
#define BIT_CONFIG_PLLEN (1<<9) // write a "1" to enable the internal PLL
#define BIT_CONFIG_WSRLOOP (1<<10) // write a "1" to connect WSROUT to WSRIN internally
enum DRSBoardConstants {
kNumberOfChannelsV2 = 10,
kNumberOfChannelsV4 = 9,
kNumberOfCalibChannelsV3 = 10,
kNumberOfCalibChannelsV4 = 9,
kNumberOfBins = 1024,
kNumberOfChips = 2,
kFrequencyCacheSize = 10,
kBSplineOrder = 4,
kPreCaliculatedBSplines = 1000,
kPreCaliculatedBSplineGroups = 5,
kNumberOfADCBins = 4096,
kBSplineXMinOffset = 20,
kMaxNumberOfClockCycles = 100,
};
enum DRSErrorCodes {
kSuccess = 0,
kInvalidTriggerSignal = -1,
kWrongChannelOrChip = -2,
kInvalidTransport = -3,
kZeroSuppression = -4,
kWaveNotAvailable = -5
};
/*---- callback class ----*/
class DRSCallback
{
public:
virtual void Progress(int value) = 0;
virtual ~DRSCallback() {};
};
/*------------------------*/
class DRSBoard;
class ResponseCalibration {
protected:
class CalibrationData {
public:
class CalibrationDataChannel {
public:
unsigned char fLimitGroup[kNumberOfBins]; //!
float fMin[kNumberOfBins]; //!
float fRange[kNumberOfBins]; //!
short fOffset[kNumberOfBins]; //!
short fGain[kNumberOfBins]; //!
unsigned short fOffsetADC[kNumberOfBins]; //!
short *fData[kNumberOfBins]; //!
unsigned char *fLookUp[kNumberOfBins]; //!
unsigned short fLookUpOffset[kNumberOfBins]; //!
unsigned char fNumberOfLookUpPoints[kNumberOfBins]; //!
float *fTempData; //!
private:
CalibrationDataChannel(const CalibrationDataChannel &c); // not implemented
CalibrationDataChannel &operator=(const CalibrationDataChannel &rhs); // not implemented
public:
CalibrationDataChannel(int numberOfGridPoints)
:fTempData(new float[numberOfGridPoints]) {
int i;
for (i = 0; i < kNumberOfBins; i++) {
fData[i] = new short[numberOfGridPoints];
}
memset(fLimitGroup, 0, sizeof(fLimitGroup));
memset(fMin, 0, sizeof(fMin));
memset(fRange, 0, sizeof(fRange));
memset(fOffset, 0, sizeof(fOffset));
memset(fGain, 0, sizeof(fGain));
memset(fOffsetADC, 0, sizeof(fOffsetADC));
memset(fLookUp, 0, sizeof(fLookUp));
memset(fLookUpOffset, 0, sizeof(fLookUpOffset));
memset(fNumberOfLookUpPoints, 0, sizeof(fNumberOfLookUpPoints));
}
~CalibrationDataChannel() {
int i;
delete fTempData;
for (i = 0; i < kNumberOfBins; i++) {
delete fData[i];
delete fLookUp[i];
}
}
};
bool fRead; //!
CalibrationDataChannel *fChannel[10]; //!
unsigned char fNumberOfGridPoints; //!
int fHasOffsetCalibration; //!
float fStartTemperature; //!
float fEndTemperature; //!
int *fBSplineOffsetLookUp[kNumberOfADCBins]; //!
float **fBSplineLookUp[kNumberOfADCBins]; //!
float fMin; //!
float fMax; //!
unsigned char fNumberOfLimitGroups; //!
static float fIntRevers[2 * kBSplineOrder - 2];
private:
CalibrationData(const CalibrationData &c); // not implemented
CalibrationData &operator=(const CalibrationData &rhs); // not implemented
public:
CalibrationData(int numberOfGridPoints);
~CalibrationData();
static int CalculateBSpline(int nGrid, float value, float *bsplines);
void PreCalculateBSpline();
void DeletePreCalculatedBSpline();
};
// General Fields
DRSBoard *fBoard;
double fPrecision;
// Fields for creating the Calibration
bool fInitialized;
bool fRecorded;
bool fFitted;
bool fOffset;
bool fCalibrationValid[2];
int fNumberOfPointsLowVolt;
int fNumberOfPoints;
int fNumberOfMode2Bins;
int fNumberOfSamples;
int fNumberOfGridPoints;
int fNumberOfXConstPoints;
int fNumberOfXConstGridPoints;
double fTriggerFrequency;
int fShowStatistics;
FILE *fCalibFile;
int fCurrentLowVoltPoint;
int fCurrentPoint;
int fCurrentSample;
int fCurrentFitChannel;
int fCurrentFitBin;
float *fResponseX[10][kNumberOfBins];
float *fResponseY;
unsigned short **fWaveFormMode3[10];
unsigned short **fWaveFormMode2[10];
unsigned short **fWaveFormOffset[10];
unsigned short **fWaveFormOffsetADC[10];
unsigned short *fSamples;
int *fSampleUsed;
float *fPntX[2];
float *fPntY[2];
float *fUValues[2];
float *fRes[kNumberOfBins];
float *fResX[kNumberOfBins];
double *fXXFit;
double *fYYFit;
double *fWWFit;
double *fYYFitRes;
double *fYYSave;
double *fXXSave;
double fGainMin;
double fGainMax;
float **fStatisticsApprox;
float **fStatisticsApproxExt;
// Fields for applying the Calibration
CalibrationData *fCalibrationData[kNumberOfChips];
private:
ResponseCalibration(const ResponseCalibration &c); // not implemented
ResponseCalibration &operator=(const ResponseCalibration &rhs); // not implemented
public:
ResponseCalibration(DRSBoard* board);
~ResponseCalibration();
void SetCalibrationParameters(int numberOfPointsLowVolt, int numberOfPoints, int numberOfMode2Bins,
int numberOfSamples, int numberOfGridPoints, int numberOfXConstPoints,
int numberOfXConstGridPoints, double triggerFrequency, int showStatistics = 0);
void ResetCalibration();
bool RecordCalibrationPoints(int chipNumber);
bool RecordCalibrationPointsV3(int chipNumber);
bool RecordCalibrationPointsV4(int chipNumber);
bool FitCalibrationPoints(int chipNumber);
bool FitCalibrationPointsV3(int chipNumber);
bool FitCalibrationPointsV4(int chipNumber);
bool OffsetCalibration(int chipNumber);
bool OffsetCalibrationV3(int chipNumber);
bool OffsetCalibrationV4(int chipNumber);
double GetTemperature(unsigned int chipIndex);
bool WriteCalibration(unsigned int chipIndex);
bool WriteCalibrationV3(unsigned int chipIndex);
bool WriteCalibrationV4(unsigned int chipIndex);
bool ReadCalibration(unsigned int chipIndex);
bool ReadCalibrationV3(unsigned int chipIndex);
bool ReadCalibrationV4(unsigned int chipIndex);
bool Calibrate(unsigned int chipIndex, unsigned int channel, float *adcWaveform,
float *uWaveform, float threshold, bool offsetCalib);
bool Calibrate(unsigned int chipIndex, unsigned int channel, unsigned short *adcWaveform, unsigned short *uWaveform,
int triggerCell, float threshold, bool offsetCalib);
bool SubtractADCOffset(unsigned int chipIndex, unsigned int channel, unsigned short *adcWaveform,
unsigned short *adcCalibratedWaveform, unsigned short newBaseLevel);
bool IsRead(int chipIndex) const { return fCalibrationValid[chipIndex]; }
double GetPrecision() const { return fPrecision; };
double GetOffsetAt(int chip,int chn,int bin) const { return fCalibrationData[chip]->fChannel[chn]->fOffset[bin]; };
double GetGainAt(int chip,int chn,int bin) const { return fCalibrationData[chip]->fChannel[chn]->fGain[bin]; };
... 336 more lines ...
|
|