| ID |
Date |
Author |
Subject |
Text |
 |
|
815
|
Fri Feb 26 21:24:39 2021 |
Tom Schneider | Trouble getting PLL to lock | Probe capacitance makes that tricky - if
I put my probe on DSPEED, I see that it starts
at approx. 2.5V then gradually decreases |
|
|
814
|
Fri Feb 26 20:32:25 2021 |
Stefan Ritt | Trouble getting PLL to lock | Can you post a scope trace of your refclk
together with DTAP, DSPEED and DENABLE?
|
|
|
813
|
Fri Feb 26 18:33:52 2021 |
Tom Schneider | Trouble getting PLL to lock | Stefan,
Thanks for responding so quickly.
Yes I have my clock source going to REFCLK+ |
|
|
812
|
Fri Feb 26 17:59:14 2021 |
Stefan Ritt | Trouble getting PLL to lock | I guess you mean "1 MHz clock at REFCLK+",
and not CLKIN, there is no CLKIN, just a
SRCLK, but that is someting else! |
|
|
811
|
Fri Feb 26 17:05:26 2021 |
Tom Schneider | Trouble getting PLL to lock | Hello,
I am working on a custom PCB design
with the DRS4 chip, and I can't get the |
|
|
810
|
Fri Feb 26 08:52:50 2021 |
Stefan Ritt | DRS spike removal for multiple waveforms | Just look at the definition of the function
below, all parameters are explained there.
In meantime we have a firmware fix to avoid |
|
|
809
|
Thu Feb 25 17:56:39 2021 |
Matthias Plum | DRS spike removal for multiple waveforms | Hi,
Is there a way that someone can
help me and my student to enable RemoveSymmetricSpikes |
|
|
808
|
Wed Jan 20 17:37:51 2021 |
Stefan Ritt | drs4 persistence | The chip itself can only sample a single
waveform, that must be done in the attached
software. The current DRSOscilloscope software |
|
|
807
|
Wed Jan 20 12:14:49 2021 |
Taegyu Lee | drs4 persistence | Dear all,
I have a question about the function that
drs4 can perform. |
|
|
806
|
Thu Dec 17 11:31:34 2020 |
Stefan Ritt | drs sources on github? | Not github, but bitbucket: https://bitbucket.org/ritt/drs4eb/src/master/
But development kind of stalled, so there |
|
|
805
|
Thu Dec 17 09:29:43 2020 |
Alex Myczko | drs sources on github? | Are there plans to add the drs software to
github? (asking because I have users @ethz.ch
that want to use it on debian,
|
|
|
804
|
Wed Oct 28 04:32:19 2020 |
Seiya Nozaki | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Stefan,
OK, it's good to hear! Thank you! |
|
|
803
|
Tue Oct 27 15:24:38 2020 |
Stefan Ritt | Timing diagram of SROUT/SRIN signal to write/read a write shift register | This is a static shift register, so you
can make the clock as slow as you want. Actually
I don't use a "clock", I just |
|
|
802
|
Tue Oct 27 15:02:09 2020 |
Seiya Nozaki | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Stefan,
Thank you for your reply. |
|
|
801
|
Tue Oct 27 13:37:23 2020 |
Stefan Ritt | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Seiya,
1) That's correct. SRIN is
ampled at the falling edge. Pleae make sure |
|
|
800
|
Wed Oct 21 15:03:13 2020 |
Seiya Nozaki | Timing diagram of SROUT/SRIN signal to write/read a write shift register | Dear Stefan,
I have questions about the timing |
|
|
799
|
Wed Oct 7 11:17:52 2020 |
Elmer Grundeman | External triggering | I will try that, thanks!
|
|
|
798
|
Wed Oct 7 10:56:03 2020 |
Stefan Ritt | External triggering | The trigger is there only to trigger the
chip, but cannot be used as a precise time
reference. If you want to measure precise |
|
|
797
|
Tue Sep 22 17:45:26 2020 |
Elmer Grundeman | External triggering | Dear all,
I had a question about timing jitter
and external triggering. |
|
|
796
|
Mon Aug 31 17:17:30 2020 |
Stefan Ritt | Channel Cascading | If you have a board with cascading option,
it should show the "combined" option
in the 2048-bin option enabled (not grayed), |
|