| ID |
Date |
Author |
Subject |
Text |
 |
|
795
|
Mon Aug 31 16:44:12 2020 |
Hans Steiger | Channel Cascading | Dear All,
I have a board with Channel Cascading
Option. I have the problem, that it seems |
|
|
794
|
Mon Aug 31 10:52:42 2020 |
Stefan Ritt | Dynamic Range Evaluation Board and Software | You cannot go below -0.5V for the inputs,
since the board does not have an internal
negative power supply, which would be necessary |
|
|
793
|
Sat Aug 29 22:00:30 2020 |
Hans Steiger | Dynamic Range Evaluation Board and Software | Dear Evaluation Board Team,
currently I am facing the problem |
|
|
792
|
Tue Jul 28 22:40:44 2020 |
Razvan Stefan Gornea | no board found | I have a very similar problem, the command
line doesn't work but the oscilloscope
program does! Tried to fix it using Zadig |
|
|
791
|
Tue May 26 12:44:16 2020 |
Stefan Ritt | Domino wave | Look at the attached picture. For simplicity,
only 4 cells are open and tracking the input
signal. Time is flowing from top to bottom. |
|
|
790
|
Tue May 26 11:10:27 2020 |
xggg | Domino wave | Hi Stefan,
According to the datasheet DRS_rev09,
the write signal is always 16 cells wide. |
|
|
789
|
Mon May 25 03:36:12 2020 |
Keita Mizukoshi | DRS4 Evaluation board control tool 'drscl' with macro file | Thank you very much. That is what I wanted.
|
|
|
788
|
Fri May 22 13:24:51 2020 |
Stefan Ritt | Type check at DOFrame.h in official software | The software is a bit outdated, I will
soon make a new release.
In meantime, you can replace that |
|
|
786
|
Fri May 22 12:53:33 2020 |
Stefan Ritt | DRS4 Evaluation board control tool 'drscl' with macro file | There is an example program in the distribution
under software/drscl/drs_exam.cpp which is
a stand-alone program to do what you need. |
|
|
785
|
Thu May 21 07:38:05 2020 |
Keita Mizukoshi | Type check at DOFrame.h in official software | Hi,
I've failured to compile official |
|
|
784
|
Thu May 21 07:18:48 2020 |
Keita Mizukoshi | DRS4 Evaluation board control tool 'drscl' with macro file | Dear experts,
I would like to use DRS4 evaluation |
|
|
783
|
Mon Mar 23 15:03:28 2020 |
Ajay Krishnamurthy | USB trigger issue | Hello,
I had forgotten to disable the
turn off the power to the USB drive on Windows |
|
|
782
|
Fri Oct 25 16:39:07 2019 |
Stefan Ritt | Computing corrected time from binary data...what is t_0,0? | t0,0 refers to the time of cell #0 of channel
#0. So basically you keep channel 0 fixed,
calculate the difference of each channel's |
|
|
781
|
Wed Oct 23 17:56:26 2019 |
John Jendzurski | Computing corrected time from binary data...what is t_0,0? | In the equations for computing the corrected
time for channels other than channel 1, does
anyone know what the term t0,0 refers |
|
|
780
|
Tue Oct 15 08:14:17 2019 |
Danyang | how to acquire the stop position with channel cascading | Thanks a lot. The problem is solved when
A3-A0 is set 1101 and srclk keeps low.
Best Regards, |
|
|
779
|
Mon Oct 14 15:27:09 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | If you configure the Write Shift Register
with 01010101b, then all you have to do after
a trigger is to set A3-A0 to 1101. The WSROUT |
|
|
778
|
Mon Oct 14 13:44:26 2019 |
Danyang | how to acquire the stop position with channel cascading | Yes, firstly I configured the chip
with 4x2048 bins by setting the Write Shift
Register to 01010101b， A3-A0 |
|
|
777
|
Mon Oct 14 12:56:13 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | Note that you have to read out the Write
Shift Register only if you do channel cascading,
e.g. configuring the chip with 4x2048 bins |
|
|
776
|
Mon Oct 14 11:45:06 2019 |
Danyang | how to acquire the stop position with channel cascading | I tried the
logic in my designed board. The results
are shown in the picture: Srout keeps low |
|
|
775
|
Mon Oct 14 10:14:46 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | You first set A3-A0, on the next clock
cycle you issue pulses on srclk, and about
10ns after each clock pulse the output shows |
|