 Mon Nov 28 22:28:34 2016, Randall Gladen, Long timing between two channels
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I don't believe I fully understand how the timing works between multiple channels on DRS4 board, even after reading the manual, but I am hoping to
measure a time difference between two channels longer than 1024/sampling rate. So far, I have written a program in Matlab to extract timing and voltage
information from the binary file to find the time difference between two channels that are set with the AND trigger logic and appear within approximately |
 Wed Nov 30 10:45:29 2016, Stefan Ritt, Long timing between two channels
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You cannot measure times longer than 1024/sampling rate.
Stefan
Randall |
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Wed Nov 30 17:48:39 2016, samridha kunwar, DRS4 Initiation
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I am having a general problem getting read back using the ROI mode. In the transparent mode everything looks good. These are the steps that I take:
1) configure register (b"11111111",addr = "1100")
2) configure write shift register (b"11111111", addr = "1101") |
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Wed Nov 30 19:05:24 2016, Stefan Ritt, DRS4 Initiation
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Uhh, there are 1000 things which might be wrong. A bit like "my car is not working, it makes strange noise". Without having a look under the
hood, there is just some wild guessing:
- Is your ROFS input at the right value? Your O-OFS? |
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Fri Dec 2 15:32:52 2016, samridha kunwar, DRS4 Initiation
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Thanks for replying Stefan.
I was more so just concerned with the steps in the firmware when I had asked. However, yes the ROFS (1.05V) and O-OFS (0.9 V was 1.3 V earlier
but, changed this becasue of ADC input requirements) are per spec, the VDD voltages are all there and input voltages are within the rails and finally the |
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Fri Dec 2 16:47:37 2016, Stefan Ritt, DRS4 Initiation
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No, I can't think of anything else. There is no intermediate addressing stage. The only thing which sometimes happens is that the QFN76 package is
not soldered correctly. If you don't have this under control, some pins might have a bad contact. You can check this by touching with a oscilloscope
probe not the PCB pads but really the pins from the side, which is a bit tricky. |
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Wed Nov 23 08:17:23 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data
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Hello,
I was running through a particular binary file containing data taken on all 4 channels of the DRS4 and printing out the value of the first time
sample for each channel (per event). While doing so, I noticed that some of these times were negative. For this dataset, channel 1 was chosen |
Thu Nov 24 13:24:26 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data 
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The code in the macro is correct. The misconception lies in the definition what "sample 0" means. Please view the attached picture. This is
simplified case with a DRS chip with only 8 cells (instead of 1024). There are two events (blue and red). In the first event, the chip is stopped at trigger
cell (tc) 2, in the second case at 5. Since the readout starts with the trigger cell, the first readout sample in the first event belongs to cell #2, the |
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Tue Nov 29 23:19:06 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data
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Hello Stefan,
Thank you for the excellent explanation and diagram. This part of the code is now much clearer to me.
My other questions pertain to the "trigger cell". Firstly, what precisely does this mean? Moreover, how does the "trigger |
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Wed Nov 30 08:53:58 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data
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The inverter chain in the DRS4 is continously running in a ring. Once you get a trigger, it is stopped. This happens in any of the 1024 cells. The last
cell which sampled a signal plus ne is called "trigger cell". In the previous diagram in event #1, the last cell sampling was "1",
so the trigger cell is "2". In event 2 (red case), the trigger cell is 5. If you would run like this, you see only the part of the waveform BEFORE |
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Fri Dec 9 04:17:46 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data
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Hello Stefan,
Many thanks for the explanations. You've cleared my confusion in this matter.
Abhishek Rajput |
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Fri Jan 13 12:58:22 2017, Gregor Kramberger, DRS software doesn't work under Windows XP SP3
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Hi all
I have a problem with running the DRSOSC under windows XP SP3. We have some hardware which is not supported under newer versions of windows and
we would like to use DRS boards along it, therefore we would higly appreciated any help in that direction. We have installed the software (V 5.03) to two |
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Fri Jan 13 13:16:09 2017, Stefan Ritt, DRS software doesn't work under Windows XP SP3
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The error probably comes from the fact that the drsosc.exe application is a 64-bit application and cannot be executed under XP any more. Unfortunately
XP is forbidden at our institute for security reasons, so I have no machine around where I could compile the executable fro XP. Another problem is the
libusb library used by drsosc.exe. Not sure if there is a XP version available any more. Have a look yourself at http://www.libusb.org/wiki/windows_backend |
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Fri Jan 13 13:50:10 2017, Stefan Ritt, DRS software doesn't work under Windows XP SP3
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Can you try that executable under XP: https://www.dropbox.com/s/j1n09afhbmh0zzu/drsosc.exe?dl=0
Gregor
Kramberger wrote:
Hi all |
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Sat Jan 28 14:11:58 2017, Danny Petschke, AND trigger problems
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Dear Stefan,
I have 2 identical pulses as a splittet signal with an amplitude of 300mV. Range is -0.5-0.5V, 5.12GSamp using the Evaluation-Board. Both signals
are triggered in AND logic. One of the signals is delayed by a fixed value of 1-50ns for testing. On increasing the trigger Level from 10% to 50% of amplitude |
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Mon Jan 30 16:37:33 2017, Stefan Ritt, AND trigger problems
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In the evaluation board we use an ADCMP601 comparator, which has a setup and hold time of 4.6 ns. So a pulse which exceeds the threshold for less than
4.6 ns will not trigger the board. If you AND two signals together, an additional constraint might apply on the coincidence pulse. This is processed in
the FPGA, but once it becomes too short, it won't trigger the board as well. I never made a real measurement of that, but I would not be suprised if |
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Tue Jan 31 01:37:35 2017, VO HONG HAI, LLD and ULD discriminations,
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Dear Stefan,
Is there any way to develop LLD and ULD discrimination in DSR-4 evaluation board?
Best regards,
V.H.Hai |
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Tue Jan 31 08:40:04 2017, Stefan Ritt, LLD and ULD discriminations,
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Not inside the board. Each channel has a single discriminator. You can select to trigger on a rising or falling edge, but you don't have two levels.
What you can do however is to make an external trigger, like using old NIM logic. You can make discrimaiton with different levels and use a coincidence
unit to combine them. Then feed the trigger into the external trigger input of the evaluation board (5V TTL level, not NIM level!). |
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Fri Feb 24 17:34:28 2017, Tarik Zengin, Passing parameters to drscl
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Hi everyone,
I wonder if there is a way to pass parameters to drscl. What I specifically want to do is calling drscl from a shell script and read/save some
data. I want to schedule a measurement. Therefore I need to call drscl from the command line using some parameters. |
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Fri Feb 24 18:35:38 2017, Stefan Ritt, Passing parameters to drscl
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This is indeed currently not implemented. But there is a simple C program drs_exam.cpp, which connects to a board and safes some data. You could modify
that program to your needs.
Stefan |
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Wed Apr 5 12:40:16 2017, Martin Petriska, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
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I would like to implement fpga firmware changes for DRS4 eval board v4 to put there posibility for standard coincidence (for example to get triger
on two short (5ns pulses from Plastic scintilator) in 100ns coincidence window), Similar but more complex was done for eval v.5 boards ( https://forge.physik.rwth-aachen.de/projects/drs4-rwth
) Im beginner in state of FPGA design, but hope it will be not so dificult to implement same functionality in eval4 board. Is there any SVN server |
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Mon Apr 10 10:48:03 2017, Stefan Ritt, DRS4 eval board v4 coincidence firmware changes for triger for short pulses
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You have to download the package for your board, which then includes also the correct firmware for your board. If you have a V4 board, your firmware
is in drs-4.0.2.tar.gz which you can download from Dropbox at https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
Martin |
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Mon Apr 10 08:50:11 2017, Giovanni Bruni, drs4 registers behaviour
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Hej everyone!
I have some questions regarding what happens to some DRS registers in some scenarios:
1. How are the registers affected by a RESET? According to the data sheet all the CONFIG REGISTER bits are initilialized to 1. But what about the |
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Mon Apr 10 10:50:57 2017, Stefan Ritt, drs4 registers behaviour
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Using the RESET line to reset registers is not a good idea since it can have some bad side-effects. The READ SHIFT register is NOT affected by RESET,
so you have to inititialize these registers differently. To set a "1"-value at a defined position, you have to follow figure 11 in the data sheet.
Once you executed that, your "1" is always at the same posiiton (namely cell #0), so after 1024 clock cycles you arrive at the same state, and |
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Mon Apr 10 13:41:41 2017, Giovanni Bruni, drs4 registers behaviour
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Hej Stefan! Thank you for your answer!
Just to be sure to have understood properly:
1. Using the RESET line should be avoided. And in any case, the CONFIG register and the WRITE SHIFT register need to be initialized "by hand" |
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Mon Apr 10 14:05:17 2017, Stefan Ritt, drs4 registers behaviour
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1. WRITE SHIFT register and CONFIG registers are initialized to "1" on power up, but if you want to change that, use A0-A3 etc. as you indicated.
2. If you address the READ SHIFT register by applyin "1011" to A0-A3, the input of the register is connected to SRIN. So in fig. 11,
you apply 1023x"0" plus 1x"1", which effectively clears the register and keeps one "1" at the last position, so on the next |
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Tue Apr 11 09:07:33 2017, Giovanni Bruni, drs4 registers behaviour
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Thank you Stefan for replying!
I have still the RESET issue in mind: how would you suggest to reset properly the DRS? Is there a particular procedure to follow instead of just
sending a negative pulse to the RESET pin? Is it preferable to turn the DRS off and then restart? |
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Tue Apr 11 09:41:44 2017, Stefan Ritt, drs4 registers behaviour
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What I do is the following: Have the RESET input unconnected. When you power up, this makes an internal reset during the power up, and that's all
you need. Then configure your registers using the sequences described in the manual. Then do not touch the RESET any more.
Stefan |
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Thu Apr 13 16:42:21 2017, Christian Farina, Stand-alone Time Calibration for PSI Board
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Hello everybody,
I was trying to create a stand-alone program that would perform a time calibration on the board. My goal would be the following.
- acquire about 10k sinus waveforms |
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Thu Apr 13 16:50:18 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board
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Hard to say. Timing calibration is quite delicate. If you start from scratch, better read this paper: https://arxiv.org/abs/1405.4975
If you try to extract the code from DRS.cpp, better read the paper, too. Probably it will not be possible to develop or extract the code without
knowing how it works. |
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Thu Apr 13 16:54:32 2017, Christian Farina, Stand-alone Time Calibration for PSI Board
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Hi Stefan,
Thank you for your reply. I have read the paper already. I looked through the code and I understand that the LTC and GTC are performed by the
AnalyzeSlope and AnalyzePeriod functions, respectively, correct? It seems to me to be a complicated business to re-write that part from scratch, at least |
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Thu Apr 13 17:02:01 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board
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Than you can try to isolate the code. Note that different SCAs might work differently. Like the DRS4 has a channel-to-channel jitter which others might
not. But you will see.
Stefan |
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Thu Apr 13 17:10:58 2017, Christian Farina, Stand-alone Time Calibration for PSI Board
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Thank you for your help Stefan. I will try to get the TC part isolated.
Stefan
Ritt wrote:
Than you can try to isolate the code. Note that different SCAs might |
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Sat Apr 15 03:48:31 2017, Strahinja Lukic, Wave rotation during transfer from the board?
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I don't know if this question is already documented elsewhere.
I am developing a DAQ code for the DRS evaluation board, v4 for a test beam experiment. I link parts of the existing DRS code as a library.
To understand the effect of various flags used in calls to the functions DRSBoard::GetTime() and DRSBoard::GetWave(), I performed several tests |
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Wed Apr 19 12:17:25 2017, Stefan Ritt, Wave rotation during transfer from the board?
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This is correct. Actually the amplitude array is rotated already inside the DRS4 chip. So the readout starts with the stop cell plus one. If you do not
do anything, the waveform is already "rotated". If you want the waveform to start with physical cell #0, you have to "unrotate" it.
Stefan |
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Thu Apr 20 06:30:13 2017, Strahinja Lukic, Wave rotation during transfer from the board?
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Thanks.
Strahinja
Stefan |
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Mon May 22 18:27:56 2017, Esperienza Giove, Invalid magic number 0000
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Hello everybody!
After some times i init my board, or if i stop the program during the acquisition, i get the error message "Invalid magic 0000". The
only way i can solve this problem is to physically disconnect and plug in again the USB cable. |
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Tue May 23 10:24:47 2017, Stefan Ritt, Invalid magic number 0000
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Under linux, many people observed that the USB connection is unstable to the evaluation board. This must be related to the linux USB stack, since my
code runs fine under MacOSX and Windows, where I use the same USB library (libusb-1.0). So I can't do anything from my side. Baybe the linux system
has some tools to reset an USB endpoint. I googled it and found some proposals here: |
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Thu May 25 20:17:41 2017, Esperienza Giove, Invalid magic number 0000
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Hello, thanks for your answer. Unluckily if i try to reset in this way it keeps hanging
musb_write: requested 10, wrote 0, errno -7 (Unknown error 18446744073709551609)
musb_read error 0 |
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Fri May 26 08:48:25 2017, Stefan Ritt, Invalid magic number 0000
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There is no other way to reset the board. As I said, people running this under Windows or MacOS are fine, so maybe this calls for a change of OS.
Esperienza
Giove wrote:
Hello, thanks for your answer. Unluckily if i try to reset in this |
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Thu May 25 20:20:57 2017, Esperienza Giove, Invalid magic number 0000
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Hello, thanks for your answer. Unluckily if i try to reset in this way it keeps hanging
musb_write: requested 10, wrote 0, errno -7 (Unknown error 18446744073709551609)
musb_read error 0 |
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Tue May 30 20:45:30 2017, Esperienza Giove, Setting input range
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Hello,
is it possible to set a completely negative input range like -1 to 0 or -0.95 to 0.05 ? |
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Tue May 30 21:00:26 2017, Stefan Ritt, Setting input range
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See elog:531
Esperienza
Giove wrote:
Hello, |
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Tue May 30 21:22:10 2017, Esperienza Giove, Setting input range
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Thank you
Stefan
Ritt wrote:
See elog:531 |
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Thu Jun 8 14:26:23 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels
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Hello,
I work with the DRS4 Evaluation Board V5 and I have a problem with the software.
I have a problem with |
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Thu Jun 8 15:52:20 2017, Stefan Ritt, AND Trigger problems with 2-3 channels
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Can you post a screenshot where I can see the channel waveforms, the configuration and the trigger settings?
Stefan
Rebecca |
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Fri Jun 9 09:44:33 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels
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Hello,
It seems that a coincidence with two fixed channels suddenly works. I don't know why.
Screenshot 1 shows the trigger settings for the coincidence with two channels. |
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Thu Jun 22 21:36:08 2017, Stefan Ritt, AND Trigger problems with 2-3 channels
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Hi,
from our screenshots I see the following:
- you have sometimes a huge oscillation in your preamplifier. Fix this first before doing any waveform recording |
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Thu Jul 6 15:10:48 2017, Esperienza Giove, Trigger setting (AND AND) OR (AND AND)
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Hello there,
is it possible to setup trigger in double AND configuration (a pair in and or other pair in and).
eg (CH 1 AND CH 2 ) OR ( CH 3 AND CH4) |
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Fri Jul 7 10:31:47 2017, Stefan Ritt, Trigger setting (AND AND) OR (AND AND)
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Unfortunately not with the current firmware.
Stefan
Esperienza |
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Wed Jul 12 04:24:39 2017, Toshihiro Nonaka, Time resolution between boards
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Hello,
I 'm using four evaluation boards v.3 to construct the multi-board DAQ system. One channel for each board is used as reference clock, then
calibrate timing offline, which allow below 10ps resolution between boards. |
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Wed Jul 12 20:16:05 2017, Stefan Ritt, Time resolution between boards
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Yes this should be possible.
Stefan
Toshihiro |
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Fri Jun 16 17:34:20 2017, Laura Gonella, Driver installation on Windows 10
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Hello,
I am trying to get a DRS4 board to run on Windows 10. I am having problems with the driver installation. I am getting the follwoing message
"There is no driver selected for the device information set or element" |
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Thu Jul 20 13:00:44 2017, Volodymyr Rodin, Driver installation on Windows 10
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Dear Laura
You need to disable driver signature enforcement. Then try again with path option.
It helped me. |
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Fri Jul 21 09:16:02 2017, Volodymyr Rodin, Time output
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Hello Stefan
I tried to convert binary to a simple txt file and found next problem - strange time output.
Here is output from little modification for read_binary.cpp (Its last output line also is strange: dT = -1.#IOns +- -1.$ps) |
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Tue Jul 25 14:47:05 2017, Volodymyr Rodin, Time output
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Hi again.
Okay, it works with 5.05 version very good and it is enough for me.
Besides, |
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Sun Aug 27 12:44:16 2017, Yuvaraj Elangovan, DRS4 version Support
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| Hi i am using DRS4 Eval Board V2, How to acquire data to a bin file using it. |
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Wed Sep 27 16:11:03 2017, Yoni Sher, Event acquisition pace for irregular timing
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Hi,
I'm running a LIDAR application that requires that every outgoing pulse be captured. My current setup firess sets of 20-50 pulses at
1 ms intervals, about 10 times a second, but only 10-20 pulses a second are captured. |
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Mon Oct 2 16:08:05 2017, Stefan Ritt, Event acquisition pace for irregular timing
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As written in the documentation, the DRS evaluaiton board has a maximum trigger capability of ~500 Hz. This is limited by the USB bus which has a finite
data transfer rate. If you build your own electronics around the chip (like many other groups are doing), you can squeeze this to a few kHz, but it is
some development effort. |