 Mon Feb 29 13:33:06 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each
|
Dear Stefan,
I daisy-chained two boards (master sn#: 2514 - slave sn#: 2513) each with 2048 samples. However, when I use drsosc and put check mark in "configure
multi-board daisy-chain" I see only 1024 samples. Namely, the first 1024 samples, the last part is missing. When I remove this check mark, I |
 Mon Feb 29 14:09:21 2016, Stefan Ritt, two DRS4 boards configuration with 2048 samples each
|
The multi-board mode has never been tested with 2048 samples, so is very likely not to work. I don't know yet how much work this will be to
fix, but I'm on a business trip the next three weeks and probably will only have time to look at it when I return.
Stefan |
|
Mon May 2 14:31:28 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each
|
Hi Stefan
Any chance you have time to fix the software for multiboard configuration with 2048 samples each. I tried 5.0.5, but drsosc still shows
only half of the waveform. |
Wed May 11 15:48:57 2016, SANDJONG Saturnin Orly, Probléme de Calibration de la DRS4 
|
Bonjour, Je suis en stage dans un laboratoire ou on utilise pour echantillonnage des données, une cartes DRS4 5GSPS avec 1024 cell, mon probléme
réside dans la partie Calibration en tension selon l'article "Novel Calibration Method for Switched Capacitor Arrays Enables Time
Measurements with Sub-Picosecond Resolution". |
|
Thu May 12 05:18:47 2016, Yu, Problem For Software Download
|
Hi
I can't download the software for windows on this website 'www.psi.ch/drs/software-download', there is some mistake when i
click on download. |
|
Thu May 12 08:16:41 2016, Stefan Ritt, Problem For Software Download
|
Can you tell me (screendump) what is the problem on the web site https://www.psi.ch/drs/software-download ?
It should redirect you to
https://www.dropbox.com/sh/qul1cgtm4x7zx13/AADKQ-qGQGdAHPu6OR3vTNY0a?dl=0 |
|
Wed May 11 04:01:14 2016, Maksat, DRS4 Macro to save events
|
Dear Stefan,
I am trying to setup DRS inside radiation enclosure and would like to write a simple script that will automatically save certain number of events.
Could you please point to me an example that can I use for Mac OS? I saw there is drs_exam.cpp in the directory but was not able to get work |
|
Thu May 12 12:38:17 2016, Stefan Ritt, DRS4 Macro to save events
|
Dear Maksat,
If your car does not run, and you call the car dealer and tell him "my car does not run", what will the car dealer ask you? Eh... ?
Right ! He will ask "what are the symptoms, what did you try, what did and what did not work". Here it's the same. "was not able to |
|
Wed Jun 1 22:29:01 2016, Dominik Neise, problems when stop cell >= 767 ??
|
Hello Stefan,
some colleages told me a story, I was neither able to confirm nor find anything in the datsheet about. According to them:
For some internal reason of the DRS4, if the “stop capacitor” of the DRS4 is >= 767, the true stop channel is one |
|
Wed Jun 1 23:16:01 2016, Stefan Ritt, problems when stop cell >= 767 ??
|
I cannot confirm the story with the "stop capacitor > 767". It can be seen from your plots that the distribution of stop cells are even,
no holes or bins with double height.
There is an issue with cell 767, but this is when one tries to do simultaneous reading/writing to the chip. This does not really work as writen |
|
Sun Jun 12 08:49:54 2016, Michael, problems of DRS4
|
Hi
I want to use DRS4 to digitize 16 channels of signals. The width of signal is about 20 ns, with frequency of 50Hz. The time differences
between these 16 signals are not constant, arranging from 3us to 0. I am confused about this in some aspects. |
|
Sun Jun 12 08:45:52 2016, Michael, problems of DRS4
|
Hi
I want to use DRS4 to digitize 16 channels of signals. The width of signal is about 20 ns, with frequency of 50Hz. The time differences
between these 16 signals are not constant, arranging from 3us to 0. I am confused about this in some aspects. |
|
Wed Jun 15 14:49:00 2016, Stefan Ritt, problems of DRS4
|
1. Simultaneous writing and reading is not possible with the DRS4 chip. The manual says differently on p. 14, but due to a bug in the chip waveforms
get clipped at the end if one does that. We hopt to fix this problem in a future version of the chip.
2. You can cascade 2,4 or 8 channels. If you cascade 8 channels and run at 1 GSPS, you digitize a window of 8 us. If you have 16 signals, you |
|
Wed Jun 29 09:10:01 2016, Stefan Ritt, Negative input signals
|
Hello everybody,
I get often asked if the DRS4 evaluation board can accomodate negative input pulses going to -1V. This is unfortunately not possible, since the
board is mainly for evaluation of the DRS4 chip and should not be seen as a complete oscilloscope with flexible input stage. So the maximum it can do is |
|
Mon Aug 29 09:36:34 2016, benjamin legeyt, increment write config register on the fly?
|
Hello,
I have a question about using the write config register to enable/disable sampling on the fly. I am looking to instrument an experiment
at EPFL where multiple short events need to be captured during a 20us period followed by an 80us quiet period during which we could read out the chip. |
|
Mon Aug 29 10:57:33 2016, Stefan Ritt, increment write config register on the fly?
|
The issue with "stopping at cell 767" would also affect this mode of operation. Furthermore, the DRS4 chip has only 10 bit register which
records in which cell the event has occured, and where the readout must be started. If you record 8 separate events, you don't know where to start
the readout. |
|
Mon Aug 29 12:18:49 2016, benjamin legeyt, increment write config register on the fly?
|
If I may trouble you for a little more information, the critical point then is that there should not be any zeroes in the write config register
while the sampling is active? In case it was unclear I would only be reading out once sampling was stopped (dwrite = 0).
As for the readout, I know that I would have to read out all 1024 samples each time, and keep track of where each channel stopped in the FPGA. |
|
Mon Aug 29 12:51:48 2016, Stefan Ritt, increment write config register on the fly?
|
The problem is when you change the write config register from 11111111 to 01111111, or from 00001111 to 00000111, then the last 256 sampels of the previous
channel (in the first case #0, in the scond #4) would be overwritten as soon as dwrite =1 again. So you loose 1/4 ef each channel.
Concerning the readout, indeed you can keep track in the FPGA, but only with a certainty of a few cells. This gives some timing inacccuracy of |
|
Thu Sep 29 17:26:13 2016, Jacob Hwang, Output Timing Drifting
|
Hello,
I have designed four DRS4 chips (36 channels) on my board running at 1GHz (REFCLK=488.28KHz) and ROI mode. All 4 chips' REFCLK, DWRITE, RSRLOAD,
and SRCLK are buffer driven by the same source. SRCLK is set to 40MHz to reduce the readout time. |
|
Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting
|
Hi Jacob,
you are missing the timing calibration. Each sampling cell has not the same width. Running at 5 GSPS, cell widths scatter from 150 ps to 250
ps. If you integrate these widhts, you get a time scale which can be off by a few ns between chips, something you see in your plot. Here is a paper which |
|
Wed Oct 5 22:43:29 2016, Will Flanagan, Timestamp for each DRS4 waveform
|
Hi DRS4 Experts,
I have been analyzing DRS4 binary data with scripts based on Stefan's (very helpful!) macro:
https://midas.psi.ch/elogs/DRS4+Forum/361 |
|
Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform
|
In the mentioned read_binary.cpp file you have the line where you read the event header
i = fread(&eh, sizeof(eh), 1, f);
The C structure eh now contains the full timestamp, and you can access it with |
|
Thu Oct 6 15:23:18 2016, Will Flanagan,
|
Hi Stefan,
That is exactly what I'm looking for. Thanks again!
Will |
|
Sun Oct 9 10:43:35 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
(Board Type:9, DRS4)
Hello,
I´m trying to reach the timig resolution of about 2.5ps as written in the manual. |
|
Sun Oct 9 11:39:18 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Can you post a screenshot of your measurement?
Stefan
Danny |
|
Mon Oct 10 11:30:37 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Hello Stefan,
Chn2 & Chn3 were used for delay-determination as you can see on the second picture.
|
|
Mon Oct 10 12:03:27 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Ok, I got it. The timing resolution is affected by the signal-to-noise ratio over the rise-time of your signal. You find the full formula herer:
https://arxiv.org/abs/1405.4975
Your sine wave input signal has a slow rise time, and therefore limits the time resolution. I reproduced your measurement with a 20 MHz sine |
|
Tue Oct 11 09:04:33 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Hello Stefan,
thanks for the paper. That makes sense. I thought about sth. like that but wasn`t sure. Couldn´t check higher frequencies (limit of my
function generator). |
|
Tue Oct 11 09:20:04 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker at the
very left side of the screen, where the yellow marker is at a different position as the others. Hint: a right-click on that slider sets it to zero. The
little streak could be some kind of external noise. |
|
Tue Oct 11 22:11:26 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
|
Thank you very much! I will check it tomorrow!
-d
Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker |
|
Wed Oct 26 21:15:35 2016, Alexey Lubinets, Problems with DRS command line
|
Hello, everybody
I have installed the software for the DRS4 Evaluation Board.
|
|
Thu Oct 27 08:29:26 2016, Stefan Ritt, Problems with DRS command line
|
[quote="Alexey Lubinets"]Hello, everybody
I have installed the software for the DRS4 Evaluation Board.
|
|
Fri Oct 28 15:02:18 2016, Simon Mendisch, Problems with DRS command line
|
[quote="Stefan Ritt"]
You are the first one describing this problem (out of ~200 people), so I guess the problem must be on your side. Have you made sure to start the DRS oscilloscope
and the Command Line Interface not at the same time? Only one program can access the board at a given time. Have you tried disconnecting and re-connecting |
|
Fri Oct 28 15:51:59 2016, Stefan Ritt, Problems with DRS command line
|
No, I absolutely have no idea. Both DRSOsc and drscl use exaclty the same code to access USB.
Stefan
|
|
Fri Nov 4 17:41:03 2016, Christian Farina, Missing Header
|
Hello everybody,
I am completely new to this, so please bear with me.
I am trying to install the applications on my laptop. I downloaded and untar-ed the drivers and applications for Linux as described in the evaluation |
|
Tue Nov 8 10:20:52 2016, Stefan Ritt, Missing Header
|
The web page from where you downloaded the software contains a sentence "requires libusb-1.0 package". Please install it. This package brings
the "usb.h" header file.
Stefan |
|
Wed Nov 9 17:19:48 2016, Christian Farina, Missing Header
|
Thank you Stefan, that was just what I needed.
Also, I have another question, if I am allowed to ask on this forum. I am trying to study how the time calibration of the DRS is done. Can you
point me to the script in which this is done? |
|
Wed Nov 9 19:49:07 2016, Stefan Ritt, Missing Header
|
Best is to read this paper: https://arxiv.org/abs/1405.4975
The source code for that is in DRS.cpp in the DRS software distribution in the function DRSBoard::CalibrateTiming()
Stefan |
|
Thu Nov 10 20:54:45 2016, Christian Farina, Missing Header
|
Hi Stefan,
I have already read the paper. I was just unsure where the calibration code was located. Thank you so much for all your help.
Christian |
|
Thu Nov 10 04:41:24 2016, Abhishek Rajput, Break Statements in DRS4 Binary to ROOT Macro
|
Hello,
I recently modified the binary to ROOT convertor written by Stefan (https://midas.psi.ch/elogs/DRS4+Forum/361) so it can decode data taken
with any channel or set of channels on the DRS4. In the process of testing this modifed version for data taken on all 4 channels, I encountered problems |
|
Thu Nov 10 09:56:04 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro
|
Hi,
fread() returns the number of bytes read and zero (I believe) if there is an end of file. So this break statement is a simple end-of-file test.
There might be other erros such as hard disk failures, but these are extremely rare. |
|
Thu Nov 10 19:24:52 2016, Abhishek Rajput, Break Statements in DRS4 Binary to ROOT Macro
|
Hello,
I am wondering why the code should be changed to i < sizeof(eh), since doesn't fread(&eh,sizeof(eh),1,f) return 1 in this scenario?
I've confirmed with a cout statement that this is the case, so this break condition will therefore always trigger as sizeof(eh) is 32 bytes. |
|
Thu Nov 10 22:07:40 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro
|
You're right, fread() return the number of objects read, so indeed it should be one if successful.
Abhishek
Rajput wrote:
Hello, |
|
Wed Mar 9 09:57:20 2016, Christian D, LabView
|
Hi,
I would like to use the DRS4 board with LabView for fast readout.
Do you know anyone who has written a VI for that? |
|
Fri Nov 18 16:38:42 2016, Gerard Montarou, LabView
|
Hello,
Did you start to write some VI to interface DRS4board with labview ?
i also have in mind to do that.I am surprised that nobody alraedy did it since there is no answer toyour question |
|
Fri Nov 18 05:52:45 2016, Kurtis Nishimura, Channel offsets in GetTime()
|
Hello,
I have a question about the GetTime() method in DRS.cpp. I understand how the DT values are applied for all channels, and I also understand
from the evaluation board manual that the timing of each channel is synchronized at sample 0, so samples should really be aligned from channel-to-channel |
|
Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime()
|
Cell 700 is arbitrary. You can choose any cell to align the channels to each other. The only requirement is that it's always the same cell for each
event. Historically, Daniel chose cell #700 more or less arbitrary, but later we found out that this works with any cell. So for the publication we went
with cell #0 (and that's why we have t_ch,0 in the paper), but cell #700 was left in the code because of lazyness. Feel free to replace 700 with any |
|
Thu Nov 24 00:40:38 2016, Alexey Lubinets, PLL did not lock
|
Hello, everybody!
I installed DRSosc and DRScl. Command line works normally (at least, it can "see" the board). But when I start the oscilloscope, I
have an error: "PLLs did not lock on USB board #0, serial number #...". In Info section I can see the board type = 9 (and in the error message |
|
Thu Nov 24 08:13:23 2016, Stefan Ritt, PLL did not lock
|
Which serial number has the board? Has it been in use before or is it a new board?
Stefan
Alexey |
|
Mon Nov 28 16:48:15 2016, Alexey Lubinets, PLL did not lock
|
The serial number is 2586. This board is about two years old, and it might be in use (but I do not know exactly).
Stefan
Ritt wrote:
Which serial number has the board? Has it been in use before or is it |
|
Mon Nov 28 16:52:38 2016, Stefan Ritt, PLL did not lock
|
Have you tried to unplug and re-plug the board a few times? According to our database, you should have three boards. Do all three show the same behavior
or only this board? In case all three show this, it could be a hint of a software problem. If two boards are good and one is bad, this would be a hint
of a hardware problem (broken board). |