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ID Date Authordown Subject Text
  49   Fri Mar 5 23:29:04 2010 Hao HuanReadout of DRS Data
  50   Tue Mar 9 23:28:45 2010 Hao HuanSerial Interface Frequency of the DRS Chip
  53   Thu Mar 11 21:37:32 2010 Hao HuanInput Bandwidth of the DRS Chip
  55   Thu Mar 18 21:38:10 2010 Hao HuanSerial Interface Frequency of the DRS Chip
  57   Sun Mar 21 02:03:44 2010 Hao HuanPLL Loop Filter Configuration
  59   Tue Mar 30 22:57:34 2010 Hao HuanROFS Configuration
  62   Fri Apr 9 17:14:45 2010 Hao HuanBaseline Variation In Data
  80   Thu May 13 19:14:27 2010 Hao HuanDVDD Problem of DRS 4
  82   Tue May 18 01:47:59 2010 Hao HuanDVDD Problem of DRS 4
  85   Wed May 19 02:24:12 2010 Hao HuanDVDD Problem of DRS 4
  87   Wed May 26 19:18:09 2010 Hao HuanHigh Frequency Input for DRS
  134   Sun Oct 23 23:32:28 2011 Hao HuanPhase Shift for ADC Readout
  140   Wed Dec 14 00:44:37 2011 Hao HuanSynchronization Delay in the Firmware for 8051 Controller
  731   Sat Feb 2 00:13:12 2019 Hans SteigerSaving Rate (only 15Acq/s)
  733   Mon Feb 4 16:42:08 2019 Hans SteigerDifferent Distances between the sampling points
  735   Mon Feb 4 17:36:49 2019 Hans SteigerDifferent Distances between the sampling points
  793   Sat Aug 29 22:00:30 2020 Hans SteigerDynamic Range Evaluation Board and Software
  795   Mon Aug 31 16:44:12 2020 Hans SteigerChannel Cascading
  374   Mon Sep 15 16:24:41 2014 Hannes WachterTiming Calibration Fail
  127   Wed Sep 7 17:28:25 2011 Hannes FriederichDRS4 and AD9222
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