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New entries since: Thu Jan 1 01:00:00 1970

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ID Date Author Subject Text   31   Sun Jan 31 23:52:15 2010 Hao Huan Failure In Flashing Xilinx PROM   30   Mon Jan 11 16:32:21 2010 Stefan Ritt normal_mode_in_drs_exam.cpp   29   Wed Dec 30 14:28:33 2009 aliyilmaz normal_mode_in_drs_exam.cpp   28   Tue Dec 22 09:07:27 2009 Stefan Ritt Trigger of DRS4   27   Tue Dec 22 01:30:55 2009 Jinhong Wang Trigger of DRS4   26   Mon Dec 21 16:52:08 2009 Stefan Ritt Trigger of DRS4   25   Mon Dec 21 10:17:05 2009 Jinhong Wang Trigger of DRS4   24   Tue Dec 15 14:38:09 2009 Stefan Ritt Trigger of DRS4   23   Mon Dec 14 10:14:16 2009 Jinhong Wang Trigger of DRS4   22   Wed Nov 4 14:42:22 2009 Stefan Ritt outline dimension of DRS4   21   Fri Oct 30 03:31:54 2009 Jinhong Wang outline dimension of DRS4   20   Mon Oct 19 12:46:12 2009 Stefan Ritt output common mode voltage of DRS4   19   Mon Oct 19 11:26:29 2009 Jinhong Wang output common mode voltage of DRS4   18   Mon Oct 19 09:13:00 2009 Stefan Ritt BIAS Pin of DRS4   17   Mon Oct 19 09:06:43 2009 Jinhong Wang BIAS Pin of DRS4   16   Fri Oct 16 10:16:10 2009 Stefan Ritt DSR4 Full Readout Mode   15   Fri Oct 16 09:51:03 2009 Jinhong Wang DSR4 Full Readout Mode   14   Wed Oct 14 23:53:05 2009 Armin Kolb DRS_exam using USB Evaluation Board with OS X   13   Wed Oct 7 17:58:20 2009 Stefan Ritt VDD switch off speed   12   Tue Oct 6 11:20:39 2009 Stefan Ritt VDD instability

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