 Fri Apr 9 20:29:45 2021, Sean Quinn, Spikes/noise sensitive to clock settings? 
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Dear DRS4 team,
I'm trying to troubleshoot some odd spike behavior. If I run the ADC and SR CLK at 16 MHz (behavior also seen at 33 MHz) we get very noisy
data (post-calibration) with periodic spikes. |
 Fri Apr 9 21:38:59 2021, Stefan Ritt, Spikes/noise sensitive to clock settings?
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elog:824
Sean
Quinn wrote:
Dear DRS4 team, |
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Fri Jun 24 09:57:36 2022, LynseyShun, Spikes/noise sensitive to clock settings?
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Hello, I now have periodic spikes in CH0 and CH1 output. How can I eliminate these spikes? I'm sorry I didn't understand your elimination
method. Please explain the method in detail. Thank you very much
Stefan |
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Tue Apr 12 10:40:36 2022, LynseyShun,
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Hello, I am Lynsey. now I set A3-A0 to 1001 in ROI mode, but only OUT0 has output, and the other seven channels(OUT1-OUT7) do not output corresponding
waveforms.
In ROI mode, can OUT0-OUT7 output sampled waveforms at the same time? |
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Tue Apr 12 10:49:27 2022, Stefan Ritt,
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A3-A0 = 1001 should be all you need to activate OUT0-OUT7. It works in our designs. Maybe double check the address lines with an oscilloscope.
Stefan
LynseyShun |
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Thu Jun 16 05:31:25 2022, LynseyShun,
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Thank you very much for your help!
Stefan
Ritt wrote:
A3-A0 = 1001 should be all you need to activate OUT0-OUT7. It works |
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Fri Mar 11 17:26:15 2022, Matias Senger, Time calibration and the C++ API
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I am using the V5 board at a fixed sampling frequency. With the `drsosc` app I have executed the time calibration at 5 GS/s (actually 5.12 GS/s). This
is how my setup looks like in the app:
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Sat Mar 12 10:13:24 2022, Stefan Ritt, Time calibration and the C++ API
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DRSBoard::GetTime is declared in DRS.h line 720.
If you want to measure timing down to ps, you need some basic knowledge, especially about signal-to-noise and risetime. This cannot be taught
in a few sentenses, needs a full lecture. As a starting point please read that papat: |
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Sat Mar 12 16:52:36 2022, Matias Senger, Time calibration and the C++ API
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Dear Stefan,
For the time of each bin I am using the values returend by `GetTime` without any assumption by my side. I did not notice before that the sampling
time is not uniform, but I see that this is already happening. This is an example plot from one of the signals I processed: |
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Mon Mar 14 08:59:51 2022, Stefan Ritt, Time calibration and the C++ API
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Looks like you have the some time calibration, not sure if it's the correct one. Sample the sine wave from the calibration clock, once with and once
without the timing calibration, then you will see if all points lie on a smooth line. Left: without timing calibration, right: with proper timing calibration:
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Tue Mar 15 13:07:50 2022, Matias Senger, Time calibration and the C++ API
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Thanks for your help. If I look into the app the behavior for the 4 channels is exactly as you show:
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Sun Mar 6 17:54:47 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
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I have connected 3 signals to the DRS4 Evaluation Board V5 which look like this in the drsosc app:
Note that here I am sampling at 5 GS/s. Using this app everything works perfect. |
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Mon Mar 7 08:45:32 2022, Stefan Ritt, Why does not trigger at higher sampling frequencies?
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Unfortunately I have not idea what the problem could be. In principle the trigger should be independent of the sampling speed, since the trigger is only
made with a discriminator and a flip-flop. The hardware must be ok since you see the trigger with the oscillocope app. All you can do is to go through
the sorce code of the oscilloscope app, especially drsosc/Osic.cpp::ScanBoards(), SetTriggerLevel(), SetTriggerPolariy() etc. to make sure you do the same |
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Tue Mar 8 00:25:56 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
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I have seen in the app that the trigger source buttons do something different than the "or" and "transparent trigger" buttons:
If I enable the setup from the right, i.e. OR in CH4 and "Enable Transparent Trigger" the app stops triggering. This is the configuration |
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Tue Mar 8 12:20:00 2022, Matias Senger, Why does not trigger at higher sampling frequencies?
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Sorry for the spam. Just want to let you know that I was able to solve the problem, it was all due to a `float` being casted as `int` in the Python binding.
Now it works like a charm.
Matias |
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Tue Mar 1 19:03:37 2022, Keita Mizukoshi, Scaler issue to evaluate live time
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Hi. I'm trying to evaluate livetime of the evaluation board with the hardware scaler. I'm facing a strange issue.
I took the rate with the function, DRS->GetScaler(int channel).
I guess that channels 0--3 mean the rate for the channel, and channel 4 means the counter of the trigger. |
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Thu Mar 3 16:14:16 2022, Stefan Ritt, Scaler issue to evaluate live time
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The scalers are read out 10x per seconds, so they have an accuracy of 10 Hz. I tried a 50 Hz pulser, and measured 40 Hz, I tried 52 Hz and measured 50
Hz. This is about what you can expect.
The scaler rate is measured after the discriminator of the trigger, so the trigger level also affects the scaler reading. If you have a 100 mV |
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Fri Mar 4 03:55:33 2022, Keita Mizukoshi, Scaler issue to evaluate live time
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Thank you very much for your explanation.
I would like to show you a pulse example ('black line is the threshold). |
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Mon Mar 7 16:37:54 2022, Stefan Ritt, Scaler issue to evaluate live time
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I tried your measurement with the DRSOscilloscope app (see below), and I measure a constant difference of 10 Hz among the whole range of 100 Hz to 3
kHz.
So I don't know what's wrong on your side. Did you try with the oscilloscope app as well? Have you checked your pulse generator? The |
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Mon Mar 7 13:38:03 2022, Radoslaw Marcinkowski, Problems with DRS4 Evaluation Board after Windows 10 upgrade - share of experiences
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Dear DRS4 Users,
I would like to share my expireinces with using of DRS4 Evaluation Board software (oscilloscope) after upgrade of Windows 10.
I had Windows 10 (Enterprise) in version from ~2016. It was working fine with DRS4 Scope software. Due to the company policy, Windows was upgraded |
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Wed Mar 2 17:25:10 2022, Matias Senger, How to convert samples to volt?
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I am using the `drscl` app. My prior experience is practically zero, sorry if this is a very naive question. When I read using `read 0 1` (channel 0,
with calibration) I get this:
``` |
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Thu Mar 3 13:47:26 2022, Stefan Ritt, How to convert samples to volt?
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The 'drscl' tool is more for experts, normal users are advised to use the DRSOsc oscilloscope.
The board has to be calibrated for a given sampling speed before calibrated data can be read out. Do that with the "calib" command,
specifying 5 for the sampling rate, 0 for the range (which is the middle between -0.5 and +0.5) and 1 for 1024 mode. If you then do "start", |
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Wed Feb 16 14:06:45 2022, Dmitry Hits, Sliders missing in drsosc
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Hi everyone,
Did anyone have a "missing sliders problem" in GUI (see attachment) accompanied by the following message in the terminal.
(drsosc:4611): Gtk-WARNING **: 14:05:11.249: Negative content width -4 (allocation 20, extents 12x12) while allocating gadget (node scale, owner |
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Sat Feb 12 13:06:56 2022, Matias Senger, Cannot trigger on pulses, have to trigger on undershoot
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I am using the DRS4 board trying to measure pulses produced by an LGAD. I have no prior experience with this board, have just installed the `drsosc`
application and am exploring. I am experiencing some strange trigger behavior. Consider the following screenshot:
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Tue Feb 15 12:02:29 2022, Stefan Ritt, Cannot trigger on pulses, have to trigger on undershoot
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The trigger comparator is a ADCMP601 unit which requires a minimum pulse width of 3-4 ns. I see that your pulses are only 1-2 ns wide. You have to make
your pulses wider in order to trigger on them.
Stefan |
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Tue Feb 15 11:59:22 2022, Alex Myczko, apt install drs4eb
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drs4b is now officially on these distributions:
https://repology.org/project/drs4eb/versions
enjoy |
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Sat Jan 15 09:13:42 2022, student_riku, I want to know about the readout
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Hello, everyone.
I'm a student in Japan.
Please forgive me if this is a very rudimentary question. |
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Sat Jan 15 10:50:47 2022, Stefan Ritt, I want to know about the readout
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student_riku
wrote:
Am I right in thinking that inputting 1 to DMODE (Bit0) in the configuration
register will connect the 1024th cell to the 1st cell? |
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Wed Jan 26 06:44:11 2022, student_riku, I want to know about the readout
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Dear Stefan
Thanks a lot.
I solved it. |
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Tue Jan 25 14:15:00 2022, Thomas M., Regarding measuring for a set time
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Hello,
I'm working on a project wherein we're looking at photomultipliers. We've already acquired a DRS4 evaluation board with the intent
of using it to gather our data. |
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Tue Jan 25 14:34:42 2022, Stefan Ritt, Regarding measuring for a set time
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drsosc is a graphical application contiously acquiring data from the board, and drscl is a command line tool for debugging, as written in the manual.
The drsosc application runs indefinitely, but I guess you refer to saving data (by hitting the "Save" button in the drsosc application).
Yes the save functionality has a number of events, since you cannot store data indefinitely, since your harddisk does not have indefinite space! |
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Tue Jan 25 14:44:49 2022, Thomas M., Regarding measuring for a set time
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Yes, you've got it exactly right. Thank you, that helps a lot!
Thomas
Stefan |
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Thu Dec 23 03:42:26 2021, Lynsey, DRS4 request assistance
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Dear Sir or Madam,
Good morning，I am using drs4 chip, and the measured fDTAP == 1/350ns, that is, fDOMINO == 1 / 350ns * 2048 == 5.8GHz.
I have three questions: |
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Mon Jan 3 17:13:41 2022, Stefan Ritt, DRS4 request assistance
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1. fDOMINO is defined as fREFCLK * 2048
2. Good values can be derived from the evaluation board schematics: C1=4.7nF, C2=1nF, R=130 Ohm
3. A "1" means a logical high level. See Wikipedia: https://en.wikipedia.org/wiki/Logic_level |
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Fri Feb 26 17:05:26 2021, Tom Schneider, Trouble getting PLL to lock
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Hello,
I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock. I'm feeding CLKIN with a 1MHz CMOS clock
(REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board. I see from the datasheet that the PLL is enabled by default, |
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Fri Feb 26 17:59:14 2021, Stefan Ritt, Trouble getting PLL to lock
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I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!
There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some
ideas: |
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Fri Feb 26 18:33:52 2021, Tom Schneider, Trouble getting PLL to lock
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Stefan,
Thanks for responding so quickly. Yes I have my clock source going to REFCLK+ (CLKIN is the signal name on my schematic). BIAS is
0.7V exactly, /RESET is high, A0-A3 are 0x0000, and the loop filter has a 4.7nF cap to GND with a 130ohm resistor + 1uF cap in parallel, just like the |
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Fri Feb 26 20:32:25 2021, Stefan Ritt, Trouble getting PLL to lock
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Can you post a scope trace of your refclk together with DTAP, DSPEED and DENABLE?
Tom
Schneider wrote:
Stefan, |
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Fri Feb 26 21:24:39 2021, Tom Schneider, Trouble getting PLL to lock
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Probe capacitance makes that tricky - if I put my probe on DSPEED, I see that it starts at approx. 2.5V then gradually decreases until it hits 0V.
DTAP decreases from 3MHz to 0 during this time.
I'll try to get something together to show you. |
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Fri Feb 26 22:12:58 2021, Stefan Ritt, Trouble getting PLL to lock
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Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB
trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2
is not really working. |
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Fri Feb 26 22:52:13 2021, Tom Schneider, Trouble getting PLL to lock
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Thats not a simple modification to my PCB, but I'll give it a try. Thanks for your help
Stefan
Ritt wrote:
Sounds to me like your REFCLK is not getting through or your PLL loop |
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Thu Mar 4 21:36:14 2021, Tom Schneider, Trouble getting PLL to lock
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I found the problem, and it had nothing to do with the CMOS clock input. As it turns out, even though I was using the default state of the config
register, I still had to write to it after powerup. Once I did that, the PLL locked immediately.
-Tom |
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Fri Mar 5 09:39:42 2021, Stefan Ritt, Trouble getting PLL to lock
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That probably depends on the way your FPGA boots. If the SRCLK signal goes high after the SRIN - even a few ns - you might clock one or two zeros
into the config register, thus disabling the PLL. Shame that I haven't thought of this before.
Stefan |
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Fri Dec 24 03:13:32 2021, Lynsey, Trouble getting PLL to lock
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I also design the circuit myself. Our problem is the same. Can we communicate？
Stefan
Ritt wrote:
I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, |
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Tue Nov 16 01:27:51 2021, Jacquelynne Vaughan, V3 board, only one channel works, all components at each channel input working
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Hi everyone,
I'm still looking through the forum for an answer to this question, but thought I'd go ahead and post anyway just in case it hasn't
been answered yet. If it has I can take this post down. |
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Tue Nov 16 08:51:14 2021, Stefan Ritt, V3 board, only one channel works, all components at each channel input working
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A V3 boards is already 10 years old and out of warranty. The software has no configuration to turn channels off except the channel buttons on the main
page on top of the sliders. I presume the channels are broked due to some overvoltage applied to them (the V5 board is better protected against over voltage).
You can send it the board for repair, but it will cost almost the same amount of money than buying a new boards. |
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Mon Sep 6 14:42:23 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
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Hi Steffan,
I have a question about how to acquire the stop channel:
Process: Configure the Write Shift Register with 00010001b to achieve 4-channel cascading, then after a trigger, |
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Sat Sep 18 15:47:50 2021, Stefan Ritt, how to acquire the stop channel with 2x4096 cascading
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The problem must be on your side, since the Write Shift Register readout works in other applications with the DRS4 chip. So I can only speculate what
could be wrong:
Do you really properly set the WSR? When you program it with 00010001b, add 8 more clock cycles and you should see the 00010001b pattern |
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Fri Nov 5 01:12:10 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
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Thanks for your advice. The problem has been solved by setting the srin again while reading out from srout.
Stefan
Ritt wrote:
The problem must be on your side, since the Write Shift Register readout |
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Mon Oct 25 18:48:04 2021, Javier Caravaca, Trigger multiple boards independently
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Hello,
I recently acquired 4 DRS4 boards and I wanted to ask if it was possible to trigger them independently from the same computer.
I know that you can daisy-chain boards and trigger them all at the same time, but in my case, each of my boards record independent events, so |
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Tue Oct 26 12:02:56 2021, Stefan Ritt, Trigger multiple boards independently
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Unfortunately an independent operation from a single computer is not supported by the software. You can try to modify the drs_exam program and extend
it. You can poll all boards in sequence and just read out that one which got a trigger, then start the loop again. But I don't know how good you are
in programming. I needs a bit of experience to do that. |
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Tue Oct 26 23:18:32 2021, Javier Caravaca, Trigger multiple boards independently
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Thank you Stefan. Actually I noticed that the source code of drs_exam was available after I started this thread, and that was the solution that
occurred to me too. I'll give that a try.
A related question is: if the 4 boards are triggering at max rate (500Hz), would the total data throughtput (of the four boards together) be |
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Wed Oct 27 08:11:42 2021, Stefan Ritt, Trigger multiple boards independently
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I'm not sure if the rate would go up to 2 kHz (not 2 GHz!). Depends how the USB hub is designed. What you can do however is to buy 4 RaspberryPis
(total cost 150$) and run everythign in parallel. The evaluation boards works nicely with the Pi's.
Javier |
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Tue Oct 26 10:41:46 2021, Mehrpad Monajem, External trigger and drs_exam
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Hi Stefan,
I have two problems regarding using the drs_exam file with external trigger: |
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Tue Oct 26 12:00:51 2021, Stefan Ritt, External trigger and drs_exam
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1. Why should your waveform start from 0 to 5ns? I don't get your point. Whenever you trigger a readout, you get a 200ns wide time window, and by
definition it starts at zero.
2. In the software distribution you have a drs_exam_2048.cpp program. Note that your board needs to be physically modified before delivery to |
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Tue Oct 26 15:05:18 2021, Mehrpad Monajem, External trigger and drs_exam
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Thanks for your reply.
1- I want to have a window size of 25.6ns instead of 200ns at 5GSPS. I have a 200khz high voltage pulser, which applies a pulse to my sample.
I want to digitize the detector signal for each pulse (each pulse has a 25.6ns period). The pulser and digitizer use same 200khz trigger signal from each |
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Thu Oct 14 15:19:00 2021, Keita Mizukoshi, livetime (or deadtime) of DRS4 evaluation board
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Dear experts,
I would like to use the DRS4 evaluation board for actual physics experiment. |
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Thu Oct 14 15:25:07 2021, Stefan Ritt, livetime (or deadtime) of DRS4 evaluation board
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The one thing you can do easily is to look at the scaler values. If one channel counts all physical events, and you have all read out events, then the
ratio give you the live/deadtime. The hardware scalers also keep running during the DRS readout.
Stefan |
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Thu Oct 14 18:03:52 2021, Keita Mizukoshi, livetime (or deadtime) of DRS4 evaluation board
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Thank you very much for your response.
Excuse me for my very stupid confirmation.
If I take N events finally and the hardware scaler value is M, the livetime is realtime*(N/M). Is this correct? |
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Thu Oct 14 18:42:31 2021, Stefan Ritt, livetime (or deadtime) of DRS4 evaluation board
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I would say not exactly, but it's a good approximation.
Keita
Mizukoshi wrote:
Thank you very much for your response. |
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Fri Oct 15 06:15:53 2021, Keita Mizukoshi, livetime (or deadtime) of DRS4 evaluation board
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Thank you very much.
Stefan
Ritt wrote:
I would say not exactly, but it's a good approximation. |
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Thu Sep 16 19:04:06 2021, Patrick Moriishi Freeman, drs_exam_multi with non-v4 boards, default configuration
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Hello,
I made a modified version drs_exam_multi.cpp, but ran into an issue when running. When I ran it, it only found the two boards with
lower serial numbers (2781 and 2879) and complained that the others (2880 and 2881) were not v4. Would there be a simple workaround for this type of thing? |
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Sat Sep 18 15:48:30 2021, Stefan Ritt, drs_exam_multi with non-v4 boards, default configuration
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Hi,
please note the the evaluation board is what it says, a board to evaluate the chip, and is not meant for a full-blown shiny multi-board DAQ channel,
so support for that is kind of limited. |