 Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4
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Hi Stefan,
in the latest DRS4 datasheet I only saw your data of the DRS4 PLL locking time for 6GSPS sampling speed, with other rows "TBD".
Have you tried those lower frequencies? According to the datasheet I think the PLLLCK should be stabily low when the PLL is locked; am I right? However |
 Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4 
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Hao Huan wrote:
Hi Stefan, |
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Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
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Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
By the way I have another question: when the default operation mode of the DRS4 chip is used, i.e. WSRIN |
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Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4
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Stefan Ritt wrote:
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Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4
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Hao Huan wrote:
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Sun Feb 21 13:41:35 2010, Stefan Ritt, Real Time Conference 2010
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Hello,
may I draw your attention to the upcoming Real Time Conference 2010, taking place in Lisbon, Portugal, May 23rd to May 28th, 2010.
http://rt2010.ipfn.ist.utl.pt/ |
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Mon Feb 15 19:43:34 2010, Ron Grazioso, Problem reading oscilloscope binary waveform output
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I have saved some waveforms using the oscilloscope application in both binary and xml. I can see that the xml file gives me proper data values
but when I try to read the binary file using IDL, it does not seem correct. This is a screen shot of the pulse I saved: |
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Tue Feb 16 09:38:59 2010, Stefan Ritt, Problem reading oscilloscope binary waveform output
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Ron Grazioso wrote:
It looks like the pulse is there but there is something corrupting the data only in binary form. |
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Wed Feb 10 02:57:55 2010, pepe sanchez lopez, Hello
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hello i am an student and i want to do my final project with drs4 board and i really can´t find how to open waveform file and how can i save or
opened many of them quickly.
if you can tell me how i will be very grateful. |
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Wed Feb 10 15:35:09 2010, Stefan Ritt, Hello
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pepe sanchez lopez wrote:
hello i am an student and i want to do my final project with drs4 board and i really can´t find |
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Sun Jan 31 23:52:15 2010, Hao Huan, Failure In Flashing Xilinx PROM
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Hi Stefan,
I have an old-version DRS4 evaluation board which doesn't have the latest firmware. I tried to flash the drs_eval1.ipf boundary
scan chain into the XCF02S PROM with Xilinx IMPACT, and the firmware seemed to go through into the PROM. However, when I started the DRS command line interface |
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Mon Feb 1 08:30:42 2010, Stefan Ritt, Failure In Flashing Xilinx PROM
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Hao Huan wrote:
Hi Stefan, |
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Wed Dec 30 14:28:33 2009, aliyilmaz, normal_mode_in_drs_exam.cpp
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Dear Mr. S. Ritt
i am Ms. student , am working with your DRS4 board to calculate the time of flight of the cosmic particle which passes
trough the hodoscope . i see the signals at scope , which is negative (i don't want to take positive side of the signal). |
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Mon Jan 11 16:32:21 2010, Stefan Ritt, normal_mode_in_drs_exam.cpp
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aliyilmaz wrote:
Dear Mr. S. Ritt |
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Mon Dec 14 10:14:16 2009, Jinhong Wang, Trigger of DRS4
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Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation
of trigger signal to stop DRS4 sampling process for readout of sampled waveform. |
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Tue Dec 15 14:38:09 2009, Stefan Ritt, Trigger of DRS4
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Jinhong Wang wrote:
Dear Mr. S. Ritt |
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Mon Dec 21 10:17:05 2009, Jinhong Wang, Trigger of DRS4
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Stefan Ritt wrote:
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Mon Dec 21 16:52:08 2009, Stefan Ritt, Trigger of DRS4
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Jinhong Wang wrote:
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Tue Dec 22 01:30:55 2009, Jinhong Wang, Trigger of DRS4
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Stefan Ritt wrote:
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Tue Dec 22 09:07:27 2009, Stefan Ritt, Trigger of DRS4
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Jinhong Wang wrote:
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Fri Oct 30 03:31:54 2009, Jinhong Wang, outline dimension of DRS4
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Wed Nov 4 14:42:22 2009, Stefan Ritt, outline dimension of DRS4
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Jinhong Wang wrote:
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Mon Oct 19 11:26:29 2009, Jinhong Wang, output common mode voltage of DRS4
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Hello Mr. Stifan.Ritt
In the DSR4 datasheet, it is mentioned
that there is an additional buffer at each analog output, this buffer shifts the the differential range of -0.5V~0.5V to 0.8V~1.8V. Does it mean that this
buffer shifts a voltage of about 1.3V for the primary differential range?
Again for the differential |
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Mon Oct 19 12:46:12 2009, Stefan Ritt, output common mode voltage of DRS4
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Jinhong Wang wrote:
Does it mean that this buffer shifts a voltage of about 1.3V for the primary differential range?
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Mon Oct 19 09:06:43 2009, Jinhong Wang, BIAS Pin of DRS4
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Dear Mr. Stefan Ritt.
Thank u for your timely response on "DSR4 Full Readout Mode", I received it from Professor
Qi An, who is my PhD supervisor. |
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Mon Oct 19 09:13:00 2009, Stefan Ritt, BIAS Pin of DRS4
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Jinhong Wang wrote:
Dear Mr. Stefan Ritt. |
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Fri Oct 16 09:51:03 2009, Jinhong Wang, DSR4 Full Readout Mode
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Hello Mr. Stefan Ritt
In DSR4 DATASHEET Rev.0.8 Page13, I noticed you metioned the samping should occur after
38 ns after the rising edge of SRCLK when the multiplexer is used. So what is suggested value(delay time between sampling and the rising edge of SRCLK) for |
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Fri Oct 16 10:16:10 2009, Stefan Ritt, DSR4 Full Readout Mode
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Jinhong Wang wrote:
Hello Mr. Stefan Ritt |
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Wed Oct 14 23:53:05 2009, Armin Kolb, DRS_exam using USB Evaluation Board with OS X
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For the users using a Macintosh,
after several hours the Evaluation Board is working on my Macintosh (intel).
1) install the development package with xcode, its on the OS X installation DVD |
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Wed Oct 7 17:58:20 2009, Stefan Ritt, VDD switch off speed
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It turned out that the VDD switch off speed plays some important role. On our VME board, we have a linear regulator, then a 4.7 uF capacitor, then the
DRS4 chip (DVDD and AVDD). When switching off the VME power, it takes quite some time to discharge the 4.7 uF capacitor, since the DRS4 chip goes into
a high impedance mode if VDD < ~1V. This gives following VDD trace: |
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Tue Oct 6 11:20:39 2009, Stefan Ritt, VDD instability
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It has turned out that the stability of the AVDD and DVDD power supplies for the DRS4 are very critical. On the evaluation board I use a REG1117-2.5,
on our VME board I use a ADP3338-2.5 for the DVDD power supply. When the domino wave is started, the power consumption of the DRS4 chip jumps up by ~40
mA, which has to be compensated by the linear regulator. Following screen shot shows what happens: |
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Thu Jul 9 09:11:03 2009, Stefan Ritt, Current problems with drs_exam.cpp
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The current version of the DRS readout example program drs_exam.cpp has two problems:
The sampling frequency cannot be changed, it will always stay in the region around 5 GSPS
The waveform obtained by GetWave
is rotated such that the first DRS cell corresponds to the first array bin
Both problems have been fixed and the fix will be contained |
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Tue Jul 7 16:39:57 2009, Stefan Ritt, Power up problem and remedy
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Maybe some of you have experienced that the DRS4 chip can get pretty hot after power up. After it's initialized the first time, the power consumption
goes back to normal. I finally found the cause of this problem and have a remedy. Here is the new paragraph from the updated data sheet:
During power-up, care has to be taken that the DENABLE and DWRITE signals are low. If not, the domino wave can get started before the power |
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Mon Apr 27 15:09:49 2009, Stefan Ritt, Amplitude and Timing calibration for DRS4 Evaluation Board
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This is a quick notification to all users of the current DRS4 evaluation board.
As you all know, the DRS4 chip needs some calibration for each individual cell which corrects the offset and the non-equidistant width in time.
While the first evaluation boards have been shipped without this calibration, the current version of the software implements a full amplitude and timing |
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Mon Feb 23 09:24:24 2009, Stefan Ritt, Rise-time measurements
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Many applications using the DRS4 need to measure fast rising signals, like for PMTs or MCPs. This short note shows the minimal rise-times which can be
measured with different input signal conditioning.
Evaluation Board
The evaluation board contains four passive transformers ADT1-1WT from Mini-Circuits to convert the single-ended input |
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Wed Feb 11 12:21:07 2009, Stefan Ritt, Corrected datasheet Rev. 0.8
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Please note the new datasheet Rev. 0.8 available from the DRS web site. It fixes the label of pin #76, which was AGND but is actualy AVDD. The
input IN8+ is located at pin #20 and not at pin #19 as described in the old table 2. |
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Wed Jan 14 12:02:04 2009, Stefan Ritt, External Trigger Input requirements
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Several people mentioned that the external trigger input (TTL) does not work on the DRS4 Evaluation Board Rev. 1.1. This is not true. The requirement
however is that the input signal must exceed approximately 1.8V. Since the input is terminated with 50 Ohms, not all TTL drivers may deliver enough current
to exceed this threshold. To verify this, the trigger signal can be monitored with an oscilloscope at test point J24. Only if the input signal exceeds |
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Wed Jan 14 13:41:44 2009, Stefan Ritt, External Trigger Input requirements
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Another tricky issue comes from the fact that the external TTL trigger and the comparator are in a logical OR. So if the comparator level is set
such that the signal is always over the threshold, the trigger is always "on" and the TTL trigger does not have any effect. It is therefore necessary |