 Tue Mar 30 22:57:34 2010, Hao Huan, ROFS Configuration
|
Hi Stefan,
according to the DRS4 datasheet, if we want an input range centered around U0, the ROFS should be 1.55V-U0. However when I read
the codes of the evaluation board application, ROFS seems to be 1.6V-1.25*U0 where the coefficient 1.25 is said to come from sampling cell charge injection |
 Thu Apr 15 13:48:40 2010, Stefan Ritt, ROFS Configuration
|
Hao Huan wrote:
Hi Stefan, |
|
Mon Apr 5 17:50:39 2010, Heejong Kim, version 1.2 evaluation board with firmware 13279?
|
Hi, Stefan,
I found that my collaborator bought 2 older version of evaluation board before.
They are the version 1.2 in plastics case with firmware
13191.
Can I upgrade the firmware from 13191 to 13279?
I'm wondering if the older version of evaluation board is working with firmware 13279.
Thanks,
Heejong
|
|
Wed Apr 14 16:34:28 2010, Stefan Ritt, version 1.2 evaluation board with firmware 13279?
|
Heejong Kim wrote:
Hi, Stefan,
I found that my collaborator bought 2 older version of evaluation board before.
They |
Tue Apr 28 11:44:07 2009, Stefan Ritt, Simple example application to read a DRS evaluation board 
|
Several people asked for s simple application to guide them in writing their own application to read out a DRS board. Such an application has been added
in software revions 2.1.1 and is attached to this message. This example program drs_exam.cpp written
in C++ does the following necessary steps to access a DRS board: |
|
Wed Apr 29 07:57:33 2009, Stefan Ritt, Simple example application to read a DRS evaluation board
|
Stefan Ritt wrote:
|
|
Mon Apr 5 17:57:41 2010, Heejong Kim, Simple example application to read a DRS evaluation board
|
Stefan Ritt wrote:
Several people asked for s simple application to guide them in writing their own application to read out |
|
Tue Apr 13 14:15:16 2010, Stefan Ritt, Simple example application to read a DRS evaluation board
|
Heejong Kim wrote:
|
|
Fri Apr 9 17:14:45 2010, Hao Huan, Baseline Variation In Data
|
Hi Stefan,
when I sample a constant input with the DRS 4 chip, there was a baseline variation showing up as a saw-tooth pattern which grows
with the absolute value of the differential input. Do you think this is the kind of baseline variation mentioned in the evaluation board manual, i.e. coming |
|
Tue Apr 13 13:56:07 2010, Stefan Ritt, Baseline Variation In Data
|
Hao Huan wrote:
Hi Stefan, |
|
Tue Apr 13 10:45:18 2010, lorenzo neri, evaluation board used like a counter
|
Hi all
|
|
Tue Apr 13 13:12:43 2010, Stefan Ritt, evaluation board used like a counter
|
lorenzo neri wrote:
Hi all |
|
Sun Mar 21 02:03:44 2010, Hao Huan, PLL Loop Filter Configuration
|
Hi Stefan,
in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF. If I want to run the Domino
wave nominally at 1GHz, i.e. with a reference clock frequency around 0.5MHz, is there any recommended loop filter configuration? Is the setup of the evaluation |
|
Mon Mar 22 09:12:19 2010, Stefan Ritt, PLL Loop Filter Configuration
|
Hao Huan wrote:
in the datasheet it says at 6GSPS the typical loop filter parameters are 220Ω, 2.2nF and 27nF. |
|
Tue Mar 9 23:28:45 2010, Hao Huan, Serial Interface Frequency of the DRS Chip
|
Hi Stefan,
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation board firmware SRCLK is
toggled at rising edges of the internal 33MHz clock, i.e. the frequency of SRCLK itself is 16.5MHz instead. Is that frequency better than 33MHz? |
|
Wed Mar 10 10:07:28 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip
|
Hao Huan wrote:
in the DRS4 datasheet I read that the optimal frequency for SRCLK is 33MHz. However in the evaluation |
|
Thu Mar 18 21:38:10 2010, Hao Huan, Serial Interface Frequency of the DRS Chip
|
Stefan Ritt wrote:
|
|
Thu Mar 18 22:10:41 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip
|
Hao Huan wrote:
|
|
Thu Mar 11 21:37:32 2010, Hao Huan, Input Bandwidth of the DRS Chip
|
Hi Stefan,
I read in the DRS datasheet that the input bandwidth if 950MHz. However, it also says the output bandwidth in the transparent
mode is 50MHz. Since in the transparent mode the input is routed to the output, does it mean the input bandwidth also gets reduced in the transparent mode? |
|
Fri Mar 12 08:04:44 2010, Stefan Ritt, Input Bandwidth of the DRS Chip
|
Hao Huan wrote:
I read in the DRS datasheet that the input bandwidth if 950MHz. However, it also says the output bandwidth |
|
Thu Mar 4 19:14:10 2010, Hao Huan, Readout of DRS Data
|
Hi Stefan,
thanks to your help I can now successfully keep the Domino wave running at a stable frequency and maintain the channel cascading
information in the Write Shift Register. (Since you told me WSR always reads and writes at the same time, I think I need to rewrite the information back |
|
Fri Mar 5 23:29:04 2010, Hao Huan, Readout of DRS Data
|
Hao Huan wrote:
Hi Stefan, |
|
Thu Mar 11 11:45:52 2010, Stefan Ritt, Readout of DRS Data
|
Hao Huan wrote:
Hi Stefan, |
|
Wed Mar 3 17:36:31 2010, Hao Huan, Initialization of the Domino Circuit
|
Hi Stefan,
I read in the datasheet that every time after power up the Domino wave in DRS4 needs to be started and stopped once to initialize
the Domino circuit. However in your firmware it seems the chip immediately goes into the idle state after reset. Is that Domino circuit initialization |
|
Wed Mar 3 17:49:30 2010, Stefan Ritt, Initialization of the Domino Circuit
|
Hao Huan wrote:
Hi Stefan, |
|
Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4
|
Hi Stefan,
in the latest DRS4 datasheet I only saw your data of the DRS4 PLL locking time for 6GSPS sampling speed, with other rows "TBD".
Have you tried those lower frequencies? According to the datasheet I think the PLLLCK should be stabily low when the PLL is locked; am I right? However |
|
Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4
|
Hao Huan wrote:
Hi Stefan, |
|
Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4
|
Stefan Ritt wrote:
|
|
Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4
|
Hao Huan wrote:
|
|
Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4
|
Stefan Ritt wrote:
|
|
Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4
|
Hao Huan wrote:
By the way I have another question: when the default operation mode of the DRS4 chip is used, i.e. WSRIN |
|
Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4
|
Stefan Ritt wrote:
|
|
Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4
|
Hao Huan wrote:
|
|
Sun Feb 21 13:41:35 2010, Stefan Ritt, Real Time Conference 2010
|
Hello,
may I draw your attention to the upcoming Real Time Conference 2010, taking place in Lisbon, Portugal, May 23rd to May 28th, 2010.
http://rt2010.ipfn.ist.utl.pt/ |
|
Mon Feb 15 19:43:34 2010, Ron Grazioso, Problem reading oscilloscope binary waveform output
|
I have saved some waveforms using the oscilloscope application in both binary and xml. I can see that the xml file gives me proper data values
but when I try to read the binary file using IDL, it does not seem correct. This is a screen shot of the pulse I saved: |
|
Tue Feb 16 09:38:59 2010, Stefan Ritt, Problem reading oscilloscope binary waveform output
|
Ron Grazioso wrote:
It looks like the pulse is there but there is something corrupting the data only in binary form. |
|
Wed Feb 10 02:57:55 2010, pepe sanchez lopez, Hello
|
hello i am an student and i want to do my final project with drs4 board and i really can´t find how to open waveform file and how can i save or
opened many of them quickly.
if you can tell me how i will be very grateful. |
|
Wed Feb 10 15:35:09 2010, Stefan Ritt, Hello
|
pepe sanchez lopez wrote:
hello i am an student and i want to do my final project with drs4 board and i really can´t find |
|
Sun Jan 31 23:52:15 2010, Hao Huan, Failure In Flashing Xilinx PROM
|
Hi Stefan,
I have an old-version DRS4 evaluation board which doesn't have the latest firmware. I tried to flash the drs_eval1.ipf boundary
scan chain into the XCF02S PROM with Xilinx IMPACT, and the firmware seemed to go through into the PROM. However, when I started the DRS command line interface |
|
Mon Feb 1 08:30:42 2010, Stefan Ritt, Failure In Flashing Xilinx PROM
|
Hao Huan wrote:
Hi Stefan, |
|
Wed Dec 30 14:28:33 2009, aliyilmaz, normal_mode_in_drs_exam.cpp
|
Dear Mr. S. Ritt
i am Ms. student , am working with your DRS4 board to calculate the time of flight of the cosmic particle which passes
trough the hodoscope . i see the signals at scope , which is negative (i don't want to take positive side of the signal). |
|
Mon Jan 11 16:32:21 2010, Stefan Ritt, normal_mode_in_drs_exam.cpp
|
aliyilmaz wrote:
Dear Mr. S. Ritt |
|
Mon Dec 14 10:14:16 2009, Jinhong Wang, Trigger of DRS4
|
Dear Mr. S. Ritt
The following is my confusion about the trigger of DRS4. It mainly concertrates on the generation
of trigger signal to stop DRS4 sampling process for readout of sampled waveform. |
|
Tue Dec 15 14:38:09 2009, Stefan Ritt, Trigger of DRS4
|
Jinhong Wang wrote:
Dear Mr. S. Ritt |
|
Mon Dec 21 10:17:05 2009, Jinhong Wang, Trigger of DRS4
|
Stefan Ritt wrote:
|
|
Mon Dec 21 16:52:08 2009, Stefan Ritt, Trigger of DRS4
|
Jinhong Wang wrote:
|
|
Tue Dec 22 01:30:55 2009, Jinhong Wang, Trigger of DRS4
|
Stefan Ritt wrote:
|
|
Tue Dec 22 09:07:27 2009, Stefan Ritt, Trigger of DRS4
|
Jinhong Wang wrote:
|
|
Fri Oct 30 03:31:54 2009, Jinhong Wang, outline dimension of DRS4
|
|
|
Wed Nov 4 14:42:22 2009, Stefan Ritt, outline dimension of DRS4
|
Jinhong Wang wrote:
|
|
Mon Oct 19 11:26:29 2009, Jinhong Wang, output common mode voltage of DRS4
|
Hello Mr. Stifan.Ritt
In the DSR4 datasheet, it is mentioned
that there is an additional buffer at each analog output, this buffer shifts the the differential range of -0.5V~0.5V to 0.8V~1.8V. Does it mean that this
buffer shifts a voltage of about 1.3V for the primary differential range?
Again for the differential |
|
Mon Oct 19 12:46:12 2009, Stefan Ritt, output common mode voltage of DRS4
|
Jinhong Wang wrote:
Does it mean that this buffer shifts a voltage of about 1.3V for the primary differential range?
|
|
Mon Oct 19 09:06:43 2009, Jinhong Wang, BIAS Pin of DRS4
|
Dear Mr. Stefan Ritt.
Thank u for your timely response on "DSR4 Full Readout Mode", I received it from Professor
Qi An, who is my PhD supervisor. |
|
Mon Oct 19 09:13:00 2009, Stefan Ritt, BIAS Pin of DRS4
|
Jinhong Wang wrote:
Dear Mr. Stefan Ritt. |