I am currently attempting to use a raspberry pi to connect to the DRS 4 board. I whenever I try to use the DRS Command Line TOol, Revision 21435 to connect to the drs board, I get the error

"musb_open: libusb_open() error -3"

"USB successfully scanned, but no boards found"

"No DRS Boards Found".

I successfully compiled the libusb driver before compiling the drs software 5.0.6, and installed all other listed packages in the install instructions.

Have you tried as root? Maybe you miss some permissions.

Stefan

Hello.

I have a simple question, can I set SetTriggerDelayNs() more than 1631 ns?

I need to set this delay to about 5 us... Can I do this? 

Thank you in advance! 

With best regards, 

Vadym

No this is not possible. But you can delay your signal externally (like with a delay cable or electronically) and then send the dealyed signal to the evaluation board for triggering.

Stefan

Thank you for your reply!

Hi!

I'm using the DRSOsc program, and I have a question that I need a bit clarified;

When triggering using AND between two channels, am I then triggering on rising/falling edge of both channels, or on the actual values?

That is, is it the change in value that it triggers on, or when the actual value goes above a certain threshold?

Using AND, it seems like I get a trigger when one (CH2) is above its trigger value (sometimes quite far above), and the other (CH1) changes to go above its trigger value. This works for my purposes, which is nice, but I just want to be sure I understand why it works. Ideally, I'd like to trigger when one of my channels is above a certain value, and the other has a rising edge above a certain value.

I'm sorry if it's a silly question! I've just noticed that the Keysight oscilloscopes I've used can only do one channel with a rising edge at a time when doing a logic trigger, and I thought the same thing might be going on in the background here (which would be ideal for my purposes).

Kind regards,

Håkan Wennlöf

Think about: How would you make a coincidence (AND) between two edges? Since an edge is infinitesimally small, there is no way to make a meaningful coincidence between edges. Therefore, the DRS4 EB firmware makes a simple AND of levels. If you trigger on rising signals and do an AND, then you get a trigger if both values are above their threshold. For falling edge trigger (arrow goes down in the trigger configuration) the board triggers when both signals are BELOW the trigger threshold. So actually the singnal which crosses the threshold last determines the timing of the trigger. I see no other way how to implement an AND.

Stefan

Hello! I'm using DRS4 evaluation board V5 with the drs command line interface,but the mannal only explained the meaning of the command--"info".And I can't get the hang of the use of other commands through "help",so is there anywhere can I learn more about other commands?Or I can only learn it through the datasheet of DRS4 chip.

Thanks!

The command line interface is more a debugging tool for experts, and you are not supposed to use it except to test the connection to the evaluation board. The programs for the user are the DRS Oscilloscope and the drs_exam.cpp example program to read out the board with your own program.

Stefan

OK!Thank you! One more question,when I use the Oscillocope ,I found that the actual speed is a constant value of 1.007G,how can change this speed.

Remove the check mark from the "Lock" box and enter a different value in the sampling speed box and hit return.

Thank you very much !! All my fault for I thought it too comlicated. Thank you sincerely!

The Display window in the Oscilloscope software shows averaging capabilites but I have not been able to activate these. Is it possible to activate averaging with the existing oscilloscope software? Thanks

This feature is not yet implemented. The (disabled) software swtich is more like a kind of a reminder to myself to work on that one day...

Dear Steffan:

We have been able to use the DRS4 using a Raspberry Pi but we have not been able to use the external trigger. What we are doing is basically comment out the code shown below (downloaded from PSI) to use the hardware trigger and uncomment the code to use the external trigger. We have not been able to get external trigger to work. Could you see what could be wrong?

Thanks

Diego

/* use following line to turn on the internal 100 MHz clock connected to all channels  */
   //b->EnableTcal(1);

   /* use following lines to enable hardware trigger on CH1 at 50 mV positive edge */

   /*
   if (b->GetBoardType() >= 8) {        // Evaluaiton Board V4&5
      b->EnableTrigger(1, 0);           // enable hardware trigger
      b->SetTriggerSource(1<<0);        // set CH1 as source
   } else if (b->GetBoardType() == 7) { // Evaluation Board V3
      b->EnableTrigger(0, 1);           // lemo off, analog trigger on
      b->SetTriggerSource(0);           // use CH1 as source
   }
   b->SetTriggerLevel(0.05);            // 0.05 V
   b->SetTriggerPolarity(false);        // positive edge
   */

   /* use following lines to set individual trigger elvels */
   //b->SetIndividualTriggerLevel(1, 0.1);
   //b->SetIndividualTriggerLevel(2, 0.2);
   //b->SetIndividualTriggerLevel(3, 0.3);
   //b->SetIndividualTriggerLevel(4, 0.4);
   //b->SetTriggerSource(15);

   b->SetTriggerDelayNs(0);             // zero ns trigger delay

   /* use following lines to enable the external trigger */
   if (b->GetBoardType() == 8) {     // Evaluaiton Board V4
      b->EnableTrigger(1, 0);           // enable hardware trigger
      b->SetTriggerSource(1<<4);        // set external trigger as source
   } else {                          // Evaluation Board V3
      b->EnableTrigger(1, 0);           // lemo on, analog trigger off
    }

Indeed the code does not work for the current evaluation board, it has been written for a previous version and never been updated. Please use following code to enable the external trigger

   /* use following lines to enable the external trigger */
   if (b->GetBoardType() >= 8) {        // Evaluaiton Board V4&5
      b->EnableTrigger(1, 0);           // enable hardware trigger
      b->SetTriggerConfig(1<<4);        // set external trigger as source
   } else {                             // Evaluation Board V3
      b->EnableTrigger(1, 0);           // lemo on, analog trigger offf
   }

Please also make sure that the signal on the external trigger input is strong enough. You need at least 2.5V at 50 Ohms, and not every driver is capable of driving 50 Ohms.

Stefan

We have been able to use the DRS4 using a Raspberry Pi but we have not been able to use the external trigger. What we are doing is basically comment out the code shown below (downloaded from PSI) to use the hardware trigger and uncomment the code to use the external trigger. We have not been able to get external trigger to work. Could you see what could be wrong?

/* use following line to turn on the internal 100 MHz clock connected to all channels  */
   //b->EnableTcal(1);

   /* use following lines to enable hardware trigger on CH1 at 50 mV positive edge */

   /*
   if (b->GetBoardType() >= 8) {        // Evaluaiton Board V4&5
      b->EnableTrigger(1, 0);           // enable hardware trigger
      b->SetTriggerSource(1<<0);        // set CH1 as source
   } else if (b->GetBoardType() == 7) { // Evaluation Board V3
      b->EnableTrigger(0, 1);           // lemo off, analog trigger on
      b->SetTriggerSource(0);           // use CH1 as source
   }
   b->SetTriggerLevel(0.05);            // 0.05 V
   b->SetTriggerPolarity(false);        // positive edge
   */

   /* use following lines to set individual trigger elvels */
   //b->SetIndividualTriggerLevel(1, 0.1);
   //b->SetIndividualTriggerLevel(2, 0.2);
   //b->SetIndividualTriggerLevel(3, 0.3);
   //b->SetIndividualTriggerLevel(4, 0.4);
   //b->SetTriggerSource(15);

   b->SetTriggerDelayNs(0);             // zero ns trigger delay

   /* use following lines to enable the external trigger */
   if (b->GetBoardType() == 8) {     // Evaluaiton Board V4
      b->EnableTrigger(1, 0);           // enable hardware trigger
      b->SetTriggerSource(1<<4);        // set external trigger as source
   } else {                          // Evaluation Board V3
      b->EnableTrigger(1, 0);           // lemo on, analog trigger off
    }

All I'm trying to do is cascade one input signal, though all available channels, so that I end up with 8*1024 bins per event.

Here is the read out on my board/chip:

Mezz. Board index:    0
DRS type:             DRS4
Board type:           8
Serial number:        2249
Firmware revision:    17662
Temperature:          35.2 C
Input range:          -0.5V...0.5V
Calibrated range:     -0.5V...0.5V
Calibrated frequency: 5.120 GHz
Status reg.:          0000001A
Control reg.:         00000010
  DMODE circular
Trigger bus:          00000000
Frequency:            5.120 GHz

What I've tried thus far:

In Osci.cpp, in the method/function  SelectSource(int board, int firstChannel, int chnSection), I added a line.. (in bold)

//----------------------------------------------------------------------------------------------------------------------------------------------

 if (b->GetBoardType() == 5 || b->GetBoardType() == 7 || b->GetBoardType() == 8) {
         
        
             if (chnSection == 2)
                b->SetChannelConfig(0, 8, 4);
             //added
             else if(chnSection == 1)
                 b->SetChannelConfig(0, 8, 2);
             //added
             else
                b->SetChannelConfig(0, 8, 8);
//----------------------------------------------------------------------------------------------------------------------------------------------

I've also tried doing settings such as SetChannelConfig(0, 8, 1);   , SetChannelConfig(0, 8, 2); , SetChannelConfig(0, 1, 2); , etc..

Which always ends up making the run fail.. and sometimes I get index errors..

As far as I understanding the program now, this is what I know:

fChannelCascading determines getChannelCascading,
this determines the  if (casc == 2) line in configDialogue.cpp, which sets:
 b->SetChannelConfig(config, 8, 4);

fChannelCascading is being set by:
 switch (nConfigChannels) {
      case 1:
         fChannelConfig = 0x01;
         fChannelCascading = 8;
         break;
      case 2:
         fChannelConfig = 0x11;
         fChannelCascading = 4;
         break;
      case 4:
         fChannelConfig = 0x55;
         fChannelCascading = 2;
         break;
      case 8:
         fChannelConfig = 0xFF;
         fChannelCascading = 1;
         break;
      default:
         printf("Invalid channel configuration\n");
         return 0;
      }

which is being set by nConfigChannels in DRS.cpp, in the method:
SetChannelConfig(int firstChannel, int lastChannel, int nConfigChannels)



SetChannelConfig is being called in the ConfigDialogue.cpp,  but the default Osci program is such that you can't do a configuration for a cascade of one signal using all the channels. At least, not that I am aware of. 

So what buttons do I need to enable, or what do I need to call, or write, so that I can cascade a signal to end up with 8*1024 bins per event?

This has had me going in circles for weeks, so thank you for your help!!!!

Sorry for my late reply, I was away for some days.

To use channel cascading, you have to physically connect one input to all eight channels. This is not possible with the evaluation board, you have to make your own board. What you could do however is to split a signal externally and feed it to all four inputs, given that the signal delay is the same for every channel. But then you will hit the hard-wired limit in Osci.cpp. This code was never foreseen to cover 8*1024 bins (since it does not make much sense with the evaluation board). Some arrays are only 2*1024 bins wide, so you would have to rewrite code at many places.

The easiest way to get what you want is to modify drs_exam.cpp. You need SetChannelConfig(0, 8, 1) as you realised correctly, and then you have to retrieve all 8 channels via b->GetWave() and concatenate them correctly.

/Stefan 

 Would it be possible to just hardcode a few lines in the SetChannelConfig in DRS.cpp method as such:

     fChannelConfig = 0x01; //gives me eight
      d = fChannelConfig | (fDominoMode << 8) | (1 << 9) | (fWSRLoop << 10) | (0xF8 << 8);

      Write(T_CTRL, REG_CHANNEL_CONFIG, &d, 2);
      fChannelDepth = 8 * (fDecimation ? kNumberOfBins/2 : kNumberOfBins);// gives eight times the bins

then modify the GetWave method/function to include another else if statement similar to  "else if (fChannelCascading == 2) {"  but would be modifidied for fChannelCascading == 8?

By, "But then you will hit the hard-wired limit in Osci.cpp" do you mean  hard-coded? Would changing the hard code just amount to resizing all of the arrays, and replacing all the '2*kNumberBins"  with '8*kNumberBins' ?

I'm afraid of drs_exam.cpp because it doesn't come with all the perks of Osci.cpp. It seems less daunting to just modify Osci.cpp then to try understanding everything I need to include in drs_exam.cpp because I'm also using an external trigger, and saving the waveform to an external text file.

Thanks!

/Jill

Sure it would be possible to code it, but it's not just a few lines. Besides Osci.cpp you have to massage DOScreen.cpp, Measurement.cpp and probably more since they all rely on the array size of the waveform. So if I would do it it would take me probably a couple of days including the debugging, which I don't have right now. Furthermore, as I said you have to combine all eight channels properly. For two channels, it's already pretty complicated (see lines 3537+ in DRS.cpp). I had to make myself a visual scheme in order to understand it correctly, which I attached. For eight channels, the write shift register (WSR) can have values 0-7, depending in which channel you got a trigger. Then you have to sort it out again to get one linear array with the proper order of the fragments. So you see, it's not just changing a few lines of code. In principle it's possible, but it's lots of work.

Best regards,

Stefan

 Stefan, thanks for your help so far. If I go with your plan A of just modifying drs_exam.cpp, is there a quick way to get it to save the data from the wave, like how osci.cpp spits out an xml file? (Ignoring the cascading aspect for now)

Thanks again :)

/Jill

Well, you have to learn C programming, I won't do it for you. drs_exam.cpp contains already code to write to the ASCII file data.txt, so you just can use that or modify it to your needs.

/Stefan

 Ha! So then the answer is no, there isn't a ready made function/method to pull out the timing and voltage,  like how it was done in osci.cpp. That's all I wanted to know. (Not whether you would write it for me! Only trying to save time!) Thanks!

/Jill

You misunderstood. The answer is yes. drs_exam.cpp contains already code to write to an ASCII file. If you actually look into the file, you see:

   f = fopen("data.txt", "w");
   ...
   b->GetTime(0, b->GetTriggerCell(0), time_array);
   ...
   b->GetWave(0, 0, wave_array[0]);
   ...
   fprintf(f, "%5.2f %6.2f\n", time_array[i], wave_array[0][i]);

which actually pulls out the timing and voltage and writes it to the file.

Hi, 

I'm trying to do the same thing (get 1 channel with 8192 bins), but I'm having some trouble with it. When I call SetChannelConfig(0, 8, 1) as suggeted, I get output that looks like noise on all readouts. Could you please explain what is supposed to happen in this case? 

I will happily write the code to combine the channels correctly (and debug it) if I can understand what needs to be done. 

(I should mention that my primary concern is a MATLAB interface which I have already written and don't mind sharing when it's complete). 

Yoni Sher

First you need a board which is modified in hardware to support channel cascading. Basically there are internal resistors which connect each input connector to two channels. You have to specify this when you order the board. Then you can use the new drs_exam_2048.cpp file contains in the git repository which correctly configures and reads out the board in two-channel cascading mode. Putting all 8 channels together is not supported by the evaluation boards.

Stefan

Hi, 

The board is modified (and checks out with the DRSScope program). Could you please point me to the drs_exam_2048.cpp file? I can't seem to fine the most up-to-date git repository....

Thanks, 

Yoni

https://bitbucket.org/ritt/drs4eb

Dear Stefan,

I am using an DRS4 board to record the signals from an plastic scintillator detector. It was working really good, yet a few day ago the signals became "not right". When I checked the signal using an oscilloscope it show the normal signals previously recorded. The signal amplitude are clearly reduced (from 0.3 in oscilloscope to lower than 0.1 in DRS4). Can you show me how to show this problem?

Thank you very much!

Best Regards,

Thien 

First thing is to do another voltage calibration. Disconnect input, "Config", "Execute Voltage Calibration". If this does not fix the problem, the board is probably broken. This can happen if you send very high input singals to the board (like >10V) and exceed the maximul allowed limit from the datasheet. In that case the board needs to be repaired. Please contact me directly (via email) so that we can make you a quote.

Best regards,
Stefan

I cannot find the EVAL board using drscl version 5.06 while the drsosc works fine. I tried 2 different eval boards and 2 different computers and the same effect. I looked under device manager at the libusb and the drs4 was there, and checked the driver which was found to be up to date.

Two people report now this problem, while this works fine at our lab. So I'm puzzled right now.

I attach two screenshots from the device manager and the Command Line interface. Can you compare it with what you see? Which is the firmware version of your evaluaiton board?

Stefan

Hi! Jim:

  It seems that I meet the same question with you ,and I am confused ,have you find out the reason about this problem?Or can you tell me how you deal with it?

Thank you very much!

chen

Hi! Stefan:

  when I change a new computer(win7,64bit),I meet a problem that the drscl app cannot found the board! It shows"USB successfully scanned,but no boards found",but the drsosc runs well . when I connect to other win7*64bits computer,only one of them runs property! Is there any driver else I need to install? 

Thank you!

Chen

This problem has been reported by several people, like elog:551

So far I could not solve it. On the computers at our lab it works find so I cannot reproduce and fix the problem. One suspicion I have is that the underlying libusb library needs to be updated. You can try to install the newest version from their website at http://libusb.info/, but I haven't tried it myself.

Stefan

I have tried about 4 computers,only one worked fine.I truly want to know how others get this fixed,can you get in touch with them?

Hello All,

I am currently trying to figure out how to properly characterize the dead time of the DRS4 board. My most recent experiment to try and answer this question involved using an external trigger that can range from 1Hz to 2MHz. I fed this trigger into the DRS4 and collected 1000 samples with no input to any channels. I repeated this across the range of my external trigger by a factor of ten [10Hz, 100Hz, 1kHz...etc]. After I had saved these runs in XML format, I looked at the difference between timestamps on the events. Attached are my findings. Can someone offer an explanation for the periodic peaks? I am new to the DRS4 and don't really understand how it works. My guess is that there is a buffer that has to be emptied every so often, but if so, the buffer emptying time varies with the frequency of the trigger. I would ideally like to be able to know the relation of the dead time to a particular setting I change on the DRS4 such as locking the sampling speed or changing external trigger frequency. 

Best,

Steven

XML is very slow to write, and you are probably limited by that. Switch to binary mode, which is much faster. You will see in the end a maximum rate of ~500 Hz, and thus a dead time of 2ms, independent of the sampling speed. Note that you have only an evaluation board, which is optimized for ease of use. If you develop your own electronics, and do optimized readout, you can bring the deadtime down to 30ns x number of samples + 2us, or 32us if you read 1024 values from one channel.

Stefan

That is extremely helpful! Many thanks. One more question; If I were to take inputs from 2 channels at once, would that scale the dead time to 64us using your example? 

Steven

For applications which are critical on the dead time, one typically uses one ADC per DRS4 channel, and thus the dead time stays at 32us. If you multiplex two DRS4 channels into one ADC channel, then it goes to 32us.

Stefan

Dear DRS4 community,

Is there a way to extract timestamps with sub-ms precision? The milliseconds of an event is clearly given when unpacking the header. I would like to determine how far apart events are when they are within the same millisecond.

Thanks,

Will

Putting sub-ms precision into the header does not make sense, since the USB transfer only happens in time-slots of about 2 ms. To get better timing, you would need a hardware time clock in the FPGA, which does not exist right now.

Best,
Stefan

Hello,

I have a question about how ROI works. From what I have read, it will only save data that ocurs some time [t_a] dictated by the user after an event is triggered as well as a small time [t_b] before the event. The technical manual seems to indicated that the deadtime assciated with operating in ROI mode can be reduced by the following factor: 

.

Where N is the number of points in the time window (ex. 2048 or 1024). Is it ok to describe this as:

Where N' is the number of samples in the ROI and N is the same as before.

For example, if I were running at 5Gsps (200ps between samples), only recording 1024 samples per event and I had an signal that lasted 2ns, that means the signal would last 10 samples. If I set the ROI to only save 20 samples around this signal, would my Deadtime go to:

? (The second portion of this equation comes from a response I recieved earlier, but I just want to make sure I understand this concept properly)

I recognize that the caveat is that this would work only if the signal was detected during acquistion, which leads to my next question. If no signals were detected in the 1024*200ps time frame in ROI mode, would the DRS4 go dead for 32us (using the factor = 1 from above equation), or would it dump the earliest events in the buffer for the more recent ones until it detects a signal? 

Finally, I assume this functionality can only be utilized with custom electornics with the DRS4, not the evaulation/demo board, please let me know if this is the case. 

Best,

Steven

N'/N is correct. The 2 us "from the response you got from me" come from the fact that after readout, you have to start the DRS4 again. During this time, the power supply usually becomes slightly unstable, and it takes on the evaluation board about 2us to stabilize it again. Tha't why I add the 2 us. If you don't care about slight offset effect, or if you make a better power supply, you dead time would be 10*30ns = 300ns for 10 samples. Starting the DRS again will take one or two clock cycles from the FPGA, which might add another 30 ns or so, depending on how you program the FPGA. So the best you can achieve for 10 samples is maybe 330 ns, if you have a really good power supply (large capacitors).

You can achieve this functionality with the evaluation board, but you would have to make a special firmware for it.

Stefan

Great! That is very helpful. 

One more question. If no signals were detected in the 1024*200ps time frame in ROI mode, would the DRS4 go dead for 32us (or 30us depending on the supply)  for, or would it dump the earliest events in the buffer for the more recent ones until it detects a signal to readout? Or rather, does filling the buffer force a readout or can it dynamically shift out old data until it detects a signal to readout. 

Steven

The DRS4 has an internal storage of 1024 capacitors. They work as a ring buffer, so at 5GSPS you can store 200ns wide signals. After 200ns, the first samples are overwritten by new samples, so you always have the last 200ns of samples stored. Once you trigger the DRS4, this buffer is frozen, and the readout of this buffer causes the dead time. No trigger, no dead time. Hope this answers your question.

Stefan

Helo
I'm building an application for reading waveforms from the DRS4 board to PC. However, I am having problems reading calibration data from EEPROM on DRS4 board. The calibration data is read through the function reference:
void DRSBoard :: ReadCalibration (void)
...
      ReadEEPROM (1, buf, 1024 * 32);
      for (i = 0; i <8; i ++)
         for (j = 0; j <1024; j ++) {
            fCellOffset [i] [j] = buf [(i * 1024 + j) * 2];
            fCellGain [i] [j] = buf [(i * 1024 + j) * 2 + 1] / 65535.0*0.4+0.7;
         }
      
      ReadEEPROM (2, buf, 1024 * 32);
      for (i = 0; i <8; i ++)
         for (j = 0; j <1024; j ++)
            fCellOffset2 [i] [j] = buf [(i * 1024 + j) * 2];
...
The Calibrate Waveform is performed by:
int DRSBoard::CalibrateWaveform(unsigned int chipIndex, unsigned char channel, unsigned short *adcWaveform, short *waveform, bool responseCalib, int triggerCell, bool adjustToClock, float threshold, bool offsetCalib)
.....
         for (j = 0; j < n_bins; j++) {
            value = adcWaveform[j] - fCellOffset[channel+chipIndex*9][(j*skip + triggerCell) % kNumberOfBins];
            value = value / fCellGain[channel+chipIndex*9][(j*skip + triggerCell) % kNumberOfBins];
            if (offsetCalib && channel != 8)
               value = value - fCellOffset2[channel+chipIndex*9][j*skip] + 32768;
...
. Because the calibration data reads incorrectly, the Calibrate Waveform does not do it.
Can read calibration data from EEPROM by any command via Oscilloscope application or DRS Command Line Interface application?
Thank you for your help!!!!

You don't have to read and calibrate the waveforms in your user code, but can rely on the DRS.cpp library to do that. Just look at the drs_exam.cpp program coming with the distribution. It uses the function b->GetWave() to retrieve the calibrated waveform. If you like, you can look into that function to learn how to apply the calibration, but I can tell you that it's a bit complicated. Since each event starts at an arbitrary stop cell in the DRS4, you have to "rotate" the calibration array. Then you do actually four calibrations in a row (cell, readout, gain and range).

Stefan

Hello everyone, 

The new read_binary.cpp code 

I will be very glad if anyone can help with the old version of read_binary.cpp code. The latest version I saw online was updated on June 30th, 2014, but I need the old version of the code to compare what changes were made in the latest version. This will help me to modify it and be able to read my data successfully. Thanks

On the software download page at https://www.psi.ch/drs/software-download you find a link to all versions of the DRS software, which is located at: https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0

Earch .tar.gz file has a date, which should help you find the correct version.

Hi, 

I would like to save the waveform in a .dat binary file using drs_exam.cpp.

I know the distributed software allows us to save as binary files with the save button, but I currently need to save multiple runs using a script.

I've seen that drs_exam.cpp can save the waveform as .txt files.

Is there any .cpp file or function that allows us to save the waveforms in binary format (.dat)?

Thank you for your help. 

You have to write the C/C++ code yourself to write data in binary or any other format. All information is present after the waveform readout in drs_exam.cpp, so it's just a matter of proper write() functions. Please consult any C/C++ handbook on how to write to files.

Hi,

we were trying to implement an automatic way to calibrate our DRS4 both in voltage and in time (we have the V5 Evaluation Board). We started from drs_exam.cpp and tried with the following lines:

/* set input range to -0.5V ... +0.5V */

b->SetInputRange(0);

b->CalibrateVolt(NULL);
b->CalibrateTiming(NULL);

While the timing calibration seems to work (we checked with drsosc executable), the voltage calibration in our test program seems not to do the same as in drsosc when pressing the button "Execute Voltage Calibration". Specifically we think that no primary calibration, secondary calibration or spike removal is applied when calling CalibrateVolt(). It seems that the methods to perform those tasks are implemented in Osci.ccp/Osci.h, but drs_exam.cpp uses objects of the class DRS (i.e. defined in DRS.cpp and DRS.h).

Is there a way to execute the voltage calibration in drs_exam.cpp in the same way performed within drsosc?

Cheers,

Alessio

Have you set the sampling frequency 

b->SetFrequency(5, true);

before the calibration?

Note there is also the "drscl" program, which is a ocmmand linke interface to the evaluation board. Start it, and do the calibration there:

then look at the code in drscl.cpp (around line 1097).

/Stefan

Hi,Stefan:

  recently,whtn I study the drs.cpp code ,I found that  the buffer[1] is char but the addr and the base_addr are all unsigned int,isn't there any problem that the addr may be cut off to 8 bits? Also ,I found that the data fpga recieved from the usb is 16 bits,so how can fpga get the true 32bits address from the PC.

The FPGA is very small, so it only has an address space of 256 bytes. Look at the definition in DRS.cpp

#define USB_CTRL_OFFSET                 0x00    /* all registers 32 bit */
#define USB_STATUS_OFFSET               0x40
#define USB_RAM_OFFSET                  0x80

The registers are 32 bits wide, but the addresses only run from 0 to 255, and thus a single byte is enough for addressing them.

Hi Stefan:

  I'm still confused that althought the 8 bits buffer is enough,the FPGA receive the command through the uc_data_i register which is 16 bits wides.As we can see in the firmware, the locbus_addr is 32 bits wides. Does it means the locbus_addr[31:8] are always '0' because the address in buffer is only 8 bits. Does it means the usrbus_status_sel and usrbus_ram_sel are also '0' all the time .

thanks!

chen

The locbus_addr is indeed 32 bits wide, since the firmware was originally derived from some firmware running in a VME crate, and the VME bus has 32 bits or addressing. So you will still find some "historic" remnants from that era. In the USB firmware, lcobus_addr[32:8] is always zero. Sorry for the confusuion.

Stefan

Hi,

we modified drs_exam.cpp to read all 4 channels from the DRS4 and apply directly the spike removal (taken from Osci.cpp) during the acquisition phase. For test purposes, we don't save the data showing spikes and we focus on the data not having spikes (even if at the end we end up having triple and quadro spikes which are not removed by the spike removal routine, but they are rare). With this modified program we wanted to characterize the noise of the DRS4, so we took 30000 events at 5GSPS, triggering on channel 1 with a 10 MHz sine wave with 100 mV_pp (trigger level set at 10 mV), while channels 2,3 and 4 were left open without any input.

We then took a look at the data and plotted the noise histograms for channels 2,3 and 4, which you can find attached (without offset correction, named zero_peak_after_spike_removal_ch*.png). For completeness, we also attached the plot from ch1 (the sine wave). The selections in time and amplitude we applied had the goal to remove the high oscillations in amplitude occurring in the first and last samples and to discard the quadro spikes we had in the data.

We see that there is a peak at 0 mV in all histograms from all channels and scanning through the data, we saw that indeed the value 0 mV is stored many times for each event, thus originating the peak we see in the histograms. We also applied an offset correction to the data (taking the average of the first three most occuring amplitudes) of channels 2 (as an example) and the problem seems to be only partially removed.

We also noticed that this peak at 0 mV is present also when we acquired the data from the DRS4 with DRSosc saving the data in binary format.

So we had the following questions:

- why is the DRS4 saving so many times the value 0 mV (exactly 0 mV)?

- is there any way (in our case through software, preferably at acquisition time) to solve this problem?

Thank you for the help and best regards,

Alessio & Davide

I note that your peak at zero is exactly twice as high as the bins left and right, so this looks to me like a binning problem in your histogramming. Maybe your bin #0 goes from -1mV to +1mV, which all other bins are just 1mW wide. Can you check that?

Stefan

Hi,

thank you for the quick reply. All the bins in the previous histograms have the same width. We also tried to plot the noise histogram for channel 2 with more bins (i.e. 1000, so that we can see almost discrete values), and the peak is still there.

Alessio & Davide

I tried the following:

- trigger on a 10 MHz sine wave on CH0, CH1 was open

- run drs_exam.cpp program and write data.txt with a few events

- imported the event into Excel

- did a histogram on (empty) CH1

What I see is a nice Gaussian distribution centered around 1mV, but with no spike around zero. See attachment. So I still believe that you have either a binning or a rounding problem. Like you round value -0.99 to +0.99 all to zero mV, and 1.00 to 1.99 mV to one mV.

Stefan

Hi Stefan,

following your example, we tried to perform the same measurement, using drs_exam and taking 1000 events. The results we obtained are in the plots attached (both in log and linear scale). We tried two different binnings:

    - the first is the same as the one used in your example, that is 0.1 mV (corresponding to the plots having 81 bins)

    - the second is a more wide binning equal to 0.35 mV, that is (2^(-11.5)) mV, 11.5 being the effective number of bits given in the DRS4 spreadsheet (corresponding to the plots having 23 bins)

With the fine binning we see that in the bin centered around 0 there is a little excess of events (the effect is more visible in the log scale histograms). This excess is not present in the wide binning case.

Is the problem we had before (and also here in the fine binning case) lying in the fact that we were trying to have bins with a width smaller than the effective resolution of the instrument (0.35 mV)?

We also noticed that in drs_exam, the values for the waveform are printed in the ASCII file with 1 digit after the decimal point, but when trying to print more digits the resolution is not improved (i.e. the decimal digits from the second one on are 0). This means that the values are rounded to a resolution of 0.1 mV when they are saved through the GetWave() routine (and in fact the member fPrecision is set to 0.1 -mV- in DRS.cpp, line 7502, and also in DRS.h, line 757, GetPrecision() returns 0.1). Why is that so? How does it reconcile with the effective number of bits giving a resolution of 0.35 mV?

Thank you,

Alessio & Davide

The DRS chip is read out with a 12 bit ADC, thus the phyical resolution is roughly 1V/4096 = 0.24 mV. I say roughly since the DRS has an analog gain of 0.98, which is corrected for. Now you have integer values which are converted into floating point numbers my multiplying them with ~0.24mV. If you then do histogramming with different bin sizes such as 0.1 mV and 0.35 mV , you get aliasing effects. The code truncates the result to 0.1 mV, which can give you also rounding artifacts. You will probalby see the same if you generate random 12 bit values and do the same histogramming. The 0.35 mV are not the RESOLUTION of the board (this is 0.24 mV as written above), but the Signal-To-Noise ratio of the DRS chip. If you measure zero volts at the input, and you make statistics over the distribution, you get an RMS of 0.35 mV.

Stefan

Dear All,

I'm troubleshooting a board which uses the DRS4 and adopts an analog front end very similar to the evaluation board. As a result, we rely on the eval board as a reference. In doing so we've encountered an issue in the manual:

The high resolution photo in Figure 1. is useful, but it seems to correspond to an older version of the board. For instance, the RF switch can't correspond to the schematics of Rev5.1 in the appendix.

Request: Could the manual be updated with a high resolution image of Rev5.1. Also, could a high resolution of the bottom side of the board be included in the manual? This is desirable since it has the version number and contact information, so it will remove any ambiguity about what board you're looking at and what schematics you should refer to.

A second question, which might be overly broad: what is the impact of installing the optional components (marked * in the schematics) on the analog front end? Why are a lot of these left uninstalled on the eval board?

Thanks,

Sean

I updated the picture in the manual with a current picture of a Rev5.1 board, and also added a picture of the bottom side. If you need a picture without the blue labels, have a look at https://www.psi.ch/drs/old-evaluation-boards at the bottom.

Here is the explanation of the optional components:

- R1, C2, R6, R29, R30 and same components for other channels: Normally the board is AC-coupled. You can make the board DC-coupled by briding C1, C9, C13, removing R6, C2, adding R1, adding R29, removing R30. The CAL signal then enters before the THS4508. We found that DC coupling gives slightly higher noise and is prone to high input DC levels, so we ship the board usually AC-coupled.

- R84 & Co. defines the hysteresis of the trigger comparators as described in the schematics

- R99-R106, R143: If soldered, the board is configured in cascading mode with 4 channels @ 2048 bins. R143 tells the FPGA that we are in this mode, so the firmware can correctly configure the DRS4

- R118 & Co. defines the MCX output level to be either 3.3V or 5V (default)

- R146-R149 connect JTAG to the uC. We planned at one point to make firmware upgrades through USB, but we never implemented that, so these resistors are not soldered.

I hope I covered everything. If I overlooked any optional component please tell me.

Cheers,
Stefan