DRS4 Forum
  DRS4 Discussion Forum, Page 6 of 45  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
ID Date Author Subject Text Attachments
  805   Thu Dec 17 09:29:43 2020 Alex Myczkodrs sources on github?Are there plans to add the drs software to
github? (asking because I have users @ethz.ch
that want to use it on debian,
  
  804   Wed Oct 28 04:32:19 2020 Seiya NozakiTiming diagram of SROUT/SRIN signal to write/read a write shift registerDear Stefan,

OK, it's good to hear! Thank you!
  
  803   Tue Oct 27 15:24:38 2020 Stefan RittTiming diagram of SROUT/SRIN signal to write/read a write shift registerThis is a static shift register, so you
can make the clock as slow as you want. Actually
I don't use a "clock", I just
  
  802   Tue Oct 27 15:02:09 2020 Seiya NozakiTiming diagram of SROUT/SRIN signal to write/read a write shift registerDear Stefan,

Thank you for your reply.
  
  801   Tue Oct 27 13:37:23 2020 Stefan RittTiming diagram of SROUT/SRIN signal to write/read a write shift registerDear Seiya,

1) That's correct. SRIN is
ampled at the falling edge. Pleae make sure
 Screenshot_2020-10-27_at_13.45.39_.png 
  800   Wed Oct 21 15:03:13 2020 Seiya NozakiTiming diagram of SROUT/SRIN signal to write/read a write shift registerDear Stefan,

I have questions about the timing
 drs4_srin_srout_srclk.pdf 
  799   Wed Oct 7 11:17:52 2020 Elmer GrundemanExternal triggeringI will try that, thanks!




  
  798   Wed Oct 7 10:56:03 2020 Stefan RittExternal triggeringThe trigger is there only to trigger the
chip, but cannot be used as a precise time
reference. If you want to measure precise
  
  797   Tue Sep 22 17:45:26 2020 Elmer GrundemanExternal triggeringDear all,

I had a question about timing jitter
and external triggering.
  
  796   Mon Aug 31 17:17:30 2020 Stefan RittChannel CascadingIf you have a board with cascading option,
it should show the "combined" option
in the 2048-bin option enabled (not grayed),
 Screenshot_2020-08-31_at_16.52.28_.png 
  795   Mon Aug 31 16:44:12 2020 Hans SteigerChannel CascadingDear All,

I have a board with Channel Cascading
Option. I have the problem, that it seems
  
  794   Mon Aug 31 10:52:42 2020 Stefan RittDynamic Range Evaluation Board and SoftwareYou cannot go below -0.5V for the inputs,
since the board does not have an internal
negative power supply, which would be necessary
  
  793   Sat Aug 29 22:00:30 2020 Hans SteigerDynamic Range Evaluation Board and SoftwareDear Evaluation Board Team,

 

currently I am facing the problem
  
  792   Tue Jul 28 22:40:44 2020 Razvan Stefan Gorneano board foundI have a very similar problem, the command
line doesn't work but the oscilloscope
program does! Tried to fix it using Zadig
 DRS4_scope.png 
  791   Tue May 26 12:44:16 2020 Stefan RittDomino waveLook at the attached picture. For simplicity,
only 4 cells are open and tracking the input
signal. Time is flowing from top to bottom.
 Screenshot_2020-05-26_at_12.43.40_.png 
  790   Tue May 26 11:10:27 2020 xgggDomino waveHi Stefan,

According to the datasheet DRS_rev09,
the write signal is always 16 cells wide.
  
  789   Mon May 25 03:36:12 2020 Keita MizukoshiDRS4 Evaluation board control tool 'drscl' with macro fileThank you very much. That is what I wanted.




  
  788   Fri May 22 13:24:51 2020 Stefan RittType check at DOFrame.h in official softwareThe software is a bit outdated, I will
soon make a new release. 

In meantime, you can replace that
  
  786   Fri May 22 12:53:33 2020 Stefan RittDRS4 Evaluation board control tool 'drscl' with macro fileThere is an example program in the distribution
under software/drscl/drs_exam.cpp which is
a stand-alone program to do what you need.
  
  785   Thu May 21 07:38:05 2020 Keita MizukoshiType check at DOFrame.h in official softwareHi,

 

I've failured to compile official
  
ELOG V3.1.5-fe60aaf