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Entry  Tue Aug 26 14:16:26 2014, Roman Gredig, binary files with more than 4 drs board ver. 5.0.2 
    Reply  Thu Oct 16 16:15:16 2014, Stefan Ritt, binary files with more than 4 drs board ver. 5.0.2 
Entry  Wed Aug 13 20:17:19 2014, Roman Gredig, binary files time calibration header in drs-5.0.2 
    Reply  Thu Oct 16 16:16:12 2014, Stefan Ritt, binary files time calibration header in drs-5.0.2 
Entry  Sun Oct 19 14:36:54 2014, Chris Tully, coverting the xml file format into binary 
Entry  Mon Nov 17 16:36:18 2014, Mickey Chiu, Raspberry Pi drsosc does not exit properly 
    Reply  Tue Nov 25 14:06:34 2014, Stefan Ritt, Raspberry Pi drsosc does not exit properly 
Entry  Fri Jan 16 13:29:05 2015, Rainer Hentges, Mac OSX Yosemite 10.10 
    Reply  Fri Jan 16 14:12:19 2015, Stefan Ritt, Mac OSX Yosemite 10.10 
Entry  Fri Feb 13 10:12:16 2015, Andrzej Grzeszczuk, drs4 and root 
Entry  Mon Mar 16 16:07:39 2015, Hermann-Josef Mathes, Running 2 instances of a DRS DAQ program 
    Reply  Tue Mar 17 02:53:26 2015, Stefan Ritt, Running 2 instances of a DRS DAQ program 
       Reply  Thu Mar 19 07:37:52 2015, Daniel Stricker-Shaver, Running 2 instances of a DRS DAQ program 
Entry  Wed Oct 15 10:14:32 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
    Reply  Wed Oct 15 10:52:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ 
       Reply  Wed Oct 15 11:34:43 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
       Reply  Wed Oct 15 12:15:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ drs_exam_multi.cpp
          Reply  Fri Apr 17 10:07:38 2015, Simon Weingarten, Clock settings in daisy chain DAQ 
             Reply  Mon Apr 20 13:08:24 2015, Stefan Ritt, Clock settings in daisy chain DAQ 
Entry  Thu Apr 9 11:46:33 2015, Felix Bachmair, DRSBoard::SetTriggerSource 
    Reply  Tue Apr 21 12:01:45 2015, Stefan Ritt, DRSBoard::SetTriggerSource 
Entry  Sun Apr 5 22:16:48 2015, Julien Wulf, DRS4 Evaluation Board Baseline/Voltage Calibration  
    Reply  Tue Apr 21 12:52:18 2015, Stefan Ritt, DRS4 Evaluation Board Baseline/Voltage Calibration  
       Reply  Tue Apr 21 13:03:38 2015, Daniel Stricker-Shaver, DRS4 Evaluation Board Baseline/Voltage Calibration  
          Reply  Tue Apr 21 13:06:39 2015, Stefan Ritt, DRS4 Evaluation Board Baseline/Voltage Calibration  
Entry  Wed May 13 01:07:36 2015, Cosmin Deaconu, DRS4 Evaluation Board + Powered USB Hub 
Entry  Wed May 13 00:52:51 2015, Cosmin Deaconu, Getting Trigger Source 
    Reply  Wed May 13 08:19:53 2015, Stefan Ritt, Getting Trigger Source 
Entry  Wed May 13 09:31:18 2015, Chenfei Yang, transparent-mode voltage tek00000_.png
    Reply  Wed May 13 09:45:51 2015, Stefan Ritt, transparent-mode voltage 
       Reply  Wed May 13 09:55:09 2015, Chenfei Yang, transparent-mode voltage 
          Reply  Wed May 13 10:16:40 2015, Stefan Ritt, transparent-mode voltage 
             Reply  Wed May 13 10:27:43 2015, Chenfei Yang, transparent-mode voltage 
             Reply  Wed May 13 12:34:49 2015, Stefan Ritt, transparent-mode voltage 
                Reply  Wed May 13 12:52:22 2015, Chenfei Yang, transparent-mode voltage 
                Reply  Wed May 13 16:13:07 2015, Chenfei Yang, transparent-mode voltage 
                   Reply  Wed May 13 16:25:24 2015, Stefan Ritt, transparent-mode voltage 
Entry  Sun May 24 09:34:27 2015, Peter Steinberg, Peculiar behavior of time values for Rev5 DRS4 EB 
    Reply  Wed Jun 3 09:07:38 2015, Stefan Ritt, Peculiar behavior of time values for Rev5 DRS4 EB 
Entry  Tue May 19 14:14:45 2015, Ilja Bekman, DRS4 firmware UCF constraints  
    Reply  Fri May 22 14:25:45 2015, Stefan Ritt, DRS4 firmware UCF constraints  firmware.zip
       Reply  Tue May 26 11:27:27 2015, Felix Bachmair, DRS4 firmware UCF constraints  
          Reply  Fri Jun 5 12:07:38 2015, Stefan Ritt, DRS4 firmware UCF constraints  
             Reply  Fri Jun 5 13:15:35 2015, Felix Bachmair, DRS4 firmware UCF constraints  
                Reply  Fri Jun 5 13:29:55 2015, Stefan Ritt, DRS4 firmware UCF constraints  
                   Reply  Fri Jun 5 13:32:03 2015, Stefan Ritt, DRS4 firmware UCF constraints  
Entry  Tue Jun 16 20:45:54 2015, Michael Buadelk, DRS4 Evaluation Board Osc Application 
    Reply  Tue Jun 16 22:26:41 2015, Stefan Ritt, DRS4 Evaluation Board Osc Application 
Entry  Thu Jun 18 17:33:05 2015, Gregor Kramberger, drs 5.03 and windows 8.1 
    Reply  Fri Jun 19 12:32:10 2015, Gregor Kramberger, drs 5.03 and windows 8.1 
Entry  Sat May 23 11:03:20 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz drs_v5_newStefan_10Hz.pngdrs_v5_newStefan_4Hz.pngdrs_v5_500_160Hz.pngdrs_5-0-0_4hz.png
    Reply  Thu Jul 2 08:53:17 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz 
Entry  Thu Jul 2 13:20:51 2015, Felix Bachmair, Creation of Object files 
    Reply  Fri Jul 3 17:13:27 2015, Stefan Ritt, Creation of Object files 
       Reply  Mon Jul 6 11:30:56 2015, Felix Bachmair, Creation of Object files 
          Reply  Mon Jul 6 19:25:27 2015, Stefan Ritt, Creation of Object files 
             Reply  Tue Jul 7 09:29:21 2015, Felix Bachmair, Creation of Object files Makefile
Entry  Mon Jul 20 09:25:38 2015, Chenfei Yang, Measure the time between different samples 
    Reply  Thu Jul 23 13:46:12 2015, Stefan Ritt, Measure the time between different samples 
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