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New entries since: Thu Jan 1 01:00:00 1970

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Mon Feb 29 13:33:06 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each        Mon Feb 29 14:09:21 2016, Stefan Ritt, two DRS4 boards configuration with 2048 samples each           Mon May 2 14:31:28 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each    Wed May 11 15:48:57 2016, SANDJONG Saturnin Orly, Probléme de Calibration de la DRS4    Thu May 12 05:18:47 2016, Yu, Problem For Software Download        Thu May 12 08:16:41 2016, Stefan Ritt, Problem For Software Download    Wed May 11 04:01:14 2016, Maksat, DRS4 Macro to save events        Thu May 12 12:38:17 2016, Stefan Ritt, DRS4 Macro to save events    Wed Jun 1 22:29:01 2016, Dominik Neise, problems when stop cell >= 767 ??        Wed Jun 1 23:16:01 2016, Stefan Ritt, problems when stop cell >= 767 ??    Sun Jun 12 08:49:54 2016, Michael, problems of DRS4    Sun Jun 12 08:45:52 2016, Michael, problems of DRS4        Wed Jun 15 14:49:00 2016, Stefan Ritt, problems of DRS4    Wed Jun 29 09:10:01 2016, Stefan Ritt, Negative input signals    Mon Aug 29 09:36:34 2016, benjamin legeyt, increment write config register on the fly?        Mon Aug 29 10:57:33 2016, Stefan Ritt, increment write config register on the fly?           Mon Aug 29 12:18:49 2016, benjamin legeyt, increment write config register on the fly?              Mon Aug 29 12:51:48 2016, Stefan Ritt, increment write config register on the fly?    Thu Sep 29 17:26:13 2016, Jacob Hwang, Output Timing Drifting        Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting    Wed Oct 5 22:43:29 2016, Will Flanagan, Timestamp for each DRS4 waveform        Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform    Thu Oct 6 15:23:18 2016, Will Flanagan,     Sun Oct 9 10:43:35 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s        Sun Oct 9 11:39:18 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s           Mon Oct 10 11:30:37 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s              Mon Oct 10 12:03:27 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s                 Tue Oct 11 09:04:33 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s                    Tue Oct 11 09:20:04 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s    Tue Oct 11 22:11:26 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s    Wed Oct 26 21:15:35 2016, Alexey Lubinets, Problems with DRS command line        Thu Oct 27 08:29:26 2016, Stefan Ritt, Problems with DRS command line           Fri Oct 28 15:02:18 2016, Simon Mendisch, Problems with DRS command line              Fri Oct 28 15:51:59 2016, Stefan Ritt, Problems with DRS command line    Fri Nov 4 17:41:03 2016, Christian Farina, Missing Header        Tue Nov 8 10:20:52 2016, Stefan Ritt, Missing Header           Wed Nov 9 17:19:48 2016, Christian Farina, Missing Header              Wed Nov 9 19:49:07 2016, Stefan Ritt, Missing Header                 Thu Nov 10 20:54:45 2016, Christian Farina, Missing Header    Thu Nov 10 04:41:24 2016, Abhishek Rajput, Break Statements in DRS4 Binary to ROOT Macro        Thu Nov 10 09:56:04 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro           Thu Nov 10 19:24:52 2016, Abhishek Rajput, Break Statements in DRS4 Binary to ROOT Macro              Thu Nov 10 22:07:40 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro    Wed Mar 9 09:57:20 2016, Christian D, LabView        Fri Nov 18 16:38:42 2016, Gerard Montarou, LabView    Fri Nov 18 05:52:45 2016, Kurtis Nishimura, Channel offsets in GetTime()        Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime()    Thu Nov 24 00:40:38 2016, Alexey Lubinets, PLL did not lock        Thu Nov 24 08:13:23 2016, Stefan Ritt, PLL did not lock           Mon Nov 28 16:48:15 2016, Alexey Lubinets, PLL did not lock              Mon Nov 28 16:52:38 2016, Stefan Ritt, PLL did not lock

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