I am using the `drscl` app. My prior experience is practically zero, sorry if this is a very naive question. When I read using `read 0 1` (channel 0, with calibration) I get this:

```
Calibration not valid for board #2946
  10    3    7    4   10    8   14    5    5    9    3    4    9    8    9    4
   3    3   12    5    5   13    3    8    1    5    0    4    8    6    6    3
...etc...
```

Why does it says that the calibration is not valid? How am I supposed to go from integers to volts?

If I run the `info` command I get this:

```
==============================
Mezz. Board index:    0
DRS type:             DRS4
Board type:           9
Serial number:        2946
Firmware revision:    30000
Temperature:          43.4 C
Input range:          -0.5V...0.5V
Calibrated range:     -0.5V...0.5V
Calibrated frequency: 0.000 GHz
Status reg.:          0000009A
Control reg.:         00000000
  DMODE circular
Trigger bus:          00000000
Frequency:            1.007 GHz
```

The 'drscl' tool is more for experts, normal users are advised to use the DRSOsc oscilloscope.

The board has to be calibrated for a given sampling speed before calibrated data can be read out. Do that with the "calib" command, specifying 5 for the sampling rate, 0 for the range (which is the middle between -0.5 and +0.5) and 1 for 1024 mode. If you then do "start", "stop", "read 0 1" you get calibrated data in mV.

Stefan

Hi everyone,

Did anyone have a "missing sliders problem" in GUI (see attachment)  accompanied by the following message in the terminal.

(drsosc:4611): Gtk-WARNING **: 14:05:11.249: Negative content width -4 (allocation 20, extents 12x12) while allocating gadget (node scale, owner GtkScale)

(drsosc:4611): Gtk-WARNING **: 14:05:11.249: Negative content width -2 (allocation 0, extents 1x1) while allocating gadget (node trough, owner GtkScale)

If yes, how did you solve it?

All ideas are appreciated!

Cheers,

Dmitry

I am using the DRS4 board trying to measure pulses produced by an LGAD. I have no prior experience with this board, have just installed the `drsosc` application and am exploring. I am experiencing some strange trigger behavior. Consider the following screenshot:

Here nothing is strange, the board is triggering on the undershoot and it is working fine, I can trigger on rising/falling edge, different levels, etc.

Now, the strange thing is that if I pull the trigger up to trigger on the pulse itself it stops triggering:

I have tried many different setups for the trigger (rising, falling edge, different levels, etc) and nothing works. In the undershoot, everything works.

I have tried with the internal test signal and it works fine:

What could be the problem?

I have run the voltage and time calibrations as suggested in the manual.

The trigger comparator is a ADCMP601 unit which requires a minimum pulse width of 3-4 ns. I see that your pulses are only 1-2 ns wide. You have to make your pulses wider in order to trigger on them.

Stefan

drs4b is now officially on these distributions:

https://repology.org/project/drs4eb/versions

enjoy

Hello, everyone.
I'm a student in Japan.
Please forgive me if this is a very rudimentary question.

Am I right in thinking that inputting 1 to DMODE (Bit0) in the configuration register will connect the 1024th cell to the 1st cell?

Also, let's assume that after sampling 1024 cells on channel 0, 200 cells are sampled in the second week.
Does the readout of 1024 cells start from cell 0?
Or does it start from the 200th cell?

Yes, as desceribed in the manual .

I don't understand what you mean by "second week". 

Normally, you run the chip continously (DMODE=1) until you receive a trigger. Then, you typically read out the chip from the stop position by using a RSRLOAD pulse (as described unter "REGION-OF-INTEREST READOUT MODE".

Stefan

Dear Stefan

Thanks a lot.

I solved it.

Hello,

I'm working on a project wherein we're looking at photomultipliers. We've already acquired a DRS4 evaluation board with the intent of using it to gather our data.

I've looked at the source code for the software with the intent of maybe writing a patch to add additional functionality. I was hoping you could answer some quick questions in that regard.

Am I correct in assuming that drsosc and drscl are functionally equivalent regarding collecting data? We want to run the DRS4-EB for a predefined amount of time. However, the DRS4 scope application seems only to run for a predefined set of measurements. Have I got that right? Is there some reason to avoid running the DRS4-EB for a predefined amount of time that I should be aware of?

Appreciate any help you can provide. Thanks!

Kind regards,

Thomas

drsosc is a graphical application contiously acquiring data from the board, and drscl is a command line tool for debugging, as written in the manual.

The drsosc application runs indefinitely, but I guess you refer to saving data (by hitting the "Save" button in the drsosc application). Yes the save functionality has a number of events, since you cannot store data indefinitely, since your harddisk does not have indefinite space!

I kind of sense that you want to convert the "number of event to save" into "number of seconds or hours to save". This is not build into the drsosc application. It's all open source, so feel free to change the code. Alternatively, you can use the drs_exam.cpp program coming with the distribution, wich is a simpel C++ program reading the board. It has a for loop over 10 events, but you can change the code easily to run for a predetermined amount of time.

Stefan

Yes, you've got it exactly right. Thank you, that helps a lot! 

Thomas

Dear Sir or Madam,

      Good morning，I am using drs4 chip, and the measured fDTAP == 1/350ns, that is, fDOMINO == 1 / 350ns * 2048 == 5.8GHz.

     I have three questions:

                              1. Is fDOMINO determined by the chip itself?

                              2. C1, C2 and R2 are TBD. I don't know how many to choose. Is there an algorithm?

                              3."Configure Write Shift Register to contain all 1's"，What, pray, is the meaning of “1's"?

                                                                                                                                                          Truely yours.

1. fDOMINO is defined as fREFCLK * 2048

2. Good values can be derived from the evaluation board schematics: C1=4.7nF, C2=1nF, R=130 Ohm

3. A "1" means a logical high level. See Wikipedia: https://en.wikipedia.org/wiki/Logic_level

Hello,

I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock.  I'm feeding CLKIN with a 1MHz CMOS clock (REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board.  I see from the datasheet that the PLL is enabled by default, so I'm not writing anything to the config register on startup.  I am just driving DENABLE high approx. 100ms after startup and looking for the PLL lock bit to go high.  When I look at DTAP, I see a 3MHz signal.  Can anyone tell me what I'm doing wrong?

-Tom

I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!

There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some ideas:

- Supply a clean differential REFCLK, I never tried one end tied to VDD/2

- Is /RESET high?

- Is BIAS at roughly 0.7V?

- Is A0-A3 different from 1111, which puts the chip in standby

- Did you double check your loop filter?

The easiest usually is to start from a running evaluation board, then compare all pins 1:1 with your board.

Stefan

Stefan,

Thanks for responding so quickly.  Yes I have my clock source going to REFCLK+ (CLKIN is the signal name on my schematic).  BIAS is 0.7V exactly, /RESET is high, A0-A3 are 0x0000, and the loop filter has a 4.7nF cap to GND with a 130ohm resistor + 1uF cap in parallel, just like the eval board.

Regarding the clock - I am not using an LVDS clock, but rather a 2.5V-level clock signal, with REFCLK- tied to 1.25V.  Sheet 9 of the datasheet states:  If no LVDS reference clock signal is available, a CMOS signal can be connected to REFCLK+ and the REFCLK input is connected to VDD/2 via a resistor divider.

Is that not a true statement?

-Tom
 

Can you post a scope trace of your refclk together with DTAP, DSPEED and DENABLE?

Probe capacitance makes that tricky - if I put my probe on DSPEED, I see that it starts at approx. 2.5V then gradually decreases until it hits 0V.  DTAP decreases from 3MHz to 0 during this time.

I'll try to get something together to show you.

Sounds to me like your REFCLK is not getting through or your PLL loop is open. Could be a bad solder connection. Try to measure signals not on the PCB trace, but directly on the DRS4 pins. Drive REFCLK with a proper LVDS signal. Maybe it's wrong what I wrote in the data sheet and the trick with VDD/2 is not really working.

Stefan

Thats not a simple modification to my PCB, but I'll give it a try.  Thanks for your help

I found the problem, and it had nothing to do with the CMOS clock input.  As it turns out, even though I was using the default state of the config register, I still had to write to it after powerup.  Once I did that, the PLL locked immediately.

-Tom

That probably depends on the way your FPGA boots. If the SRCLK signal goes high after the SRIN - even a few ns - you might clock one or two zeros into the config register, thus disabling the PLL. Shame that I haven't thought of this before.

Stefan

I also design the circuit myself. Our problem is the same. Can we communicate？

Hi everyone,

I'm still looking through the forum for an answer to this question, but thought I'd go ahead and post anyway just in case it hasn't been answered yet. If it has I can take this post down.

I have a V3 board, and as far as I can tell only channel 2 gives an output. If I enable other channels using the DRS Oscilloscope software, they do show static but will not show a signal if I connect one to them (e.g. a series of subsequent square waves). A technician and I took the board out and tested all the components leading up to the microcontrollers for each channel, and everything seemed to be working fine. I thought maybe it was configured to only have one channel read an output, but I looked through the Config panel in the software and nothing seemed to indicate that.

I am a novice, and maybe I'm missing something that I didn't see in the manual. I can post screenshots if needed!

Thank you for your help!

A V3 boards is already 10 years old and out of warranty. The software has no configuration to turn channels off except the channel buttons on the main page on top of the sliders. I presume the channels are broked due to some overvoltage applied to them (the V5 board is better protected against over voltage). You can send it the board for repair, but it will cost almost the same amount of money than buying a new boards.

Regards,
Stefan

Hi Steffan,

    I have a question about how to acquire the stop channel: 

    Process:   Configure the Write Shift Register with 00010001b to achieve 4-channel cascading, then after a trigger, set A3-A0 to 1101, sclk keeps 0.

    Result:   the WSROUT pin keeps 0, the SROUT pin has no clock pulse as written in datasheet, but keeps always 1 or 0. It can be seen the stop channel is channel 0 or channel 1, but no situation to represtent channel 3 or channel 4. And if set sclk with 8 pulses, the  WSROUT and SROUT both keep 0.

    What should I pay attention to? Looking forward to your reply.

Jiaolong 

The problem must be on your side, since the Write Shift Register readout works in other applications with the DRS4 chip. So I can only speculate what could be wrong:

• Do you really properly set the WSR? When you program it with 00010001b, add 8 more clock cycles and you should see the 00010001b pattern at WSROUT.
• Do all tests with an oscilloscope, to avoid potential problems in your FPGA firmware (like an input configures as an output by mistake).
• DWRITE must be high to see the contents of the WSR at the WSROUT pin, maybe that’s your mistake, see datasheet p 5 of 16.
• To see the contents of the WSR at SROUT, A0-3 must be 1101b, please check with your oscilloscope
• The addresses A0-A3 are simply connected to a multiplexer, so no clock is necessary after the addresses change

Stefan

Thanks for your advice. The problem has been solved by setting the srin again while reading out from srout.

Hello,

I recently acquired 4 DRS4 boards and I wanted to ask if it was possible to trigger them independently from the same computer.

I know that you can daisy-chain boards and trigger them all at the same time, but in my case, each of my boards record independent events, so I want them to trigger when trigger conditions are met in each board. I currently use the provided DRSOSC software, that can trigger on only the board that is being displayed at that moment. I tried opening several instances of DRSOSC to associate each to each board, but that is not possible since the second instance already does not find the boards. I wonder if there is a way of triggering from each board independently without having to use four computers.

Thank you,

Javier.

Unfortunately an independent operation from a single computer is not supported by the software. You can try to modify the drs_exam program and extend it. You can poll all boards in sequence and just read out that one which got a trigger, then start the loop again. But I don't know how good you are in programming. I needs a bit of experience to do that.

Stefan

Thank you Stefan. Actually I noticed that the source code of drs_exam was available after I started this thread, and that was the solution that occurred to me too. I'll give that a try.

A related question is: if the 4 boards are triggering at max rate (500Hz), would the total data throughtput (of the four boards together) be 2GHz (500Hz x 4)? Or is the limitation on the readout, rather than the triggering?

Best,

Javier.

I'm not sure if the rate would go up to 2 kHz (not 2 GHz!). Depends how the USB hub is designed. What you can do however is to buy 4 RaspberryPis (total cost 150$) and run everythign in parallel. The evaluation boards works nicely with the Pi's.

Hi Stefan,

I have two problems regarding using the drs_exam file with external trigger:

1- I connected a 200Khz signal with 20ns rising edge, 50 ohm load, and 27% duty cycle as an external trigger. The output of the drs_exam file starts from 0 to 200ns. Since I use an external trigger, I think it should be starting from 0 to 5ns and then again starting from 0. Could you please tell me where the problem is?

2- How is it possible to change from 1024 to 2048 bins in the drs_exam example?

You can find my code in the attachment.

Best regards,
Mehrpad

1. Why should your waveform start from 0 to 5ns? I don't get your point. Whenever you trigger a readout, you get a 200ns wide time window, and by definition it starts at zero.

2. In the software distribution you have a drs_exam_2048.cpp program. Note that your board needs to be physically modified before delivery to switch to 2048 bins.

Best,
Stefan

Thanks for your reply.

1- I want to have a window size of 25.6ns instead of 200ns at 5GSPS. I have a 200khz high voltage pulser, which applies a pulse to my sample. I want to digitize the detector signal for each pulse (each pulse has a 25.6ns period). The pulser and digitizer use same 200khz trigger signal from each channel of the signal generator.

2- My DRS board has a 2048 combined stick on it. But the software distribution that I have doesn't contain the drs_exam_2048.cpp program. Could you please send the link that I can download this program? I can't find it under the link below.

link: https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0

Best regards,

Mehrpad

Dear experts,

I would like to use the DRS4 evaluation board for actual physics experiment.

I made a CUI script based on the drs_exam, https://github.com/mzks/drs4_tools/blob/main/build/source/drscmd.cpp.

In this framework, how can we obtain DAQ livetime (or deadtime)?

Has some function already provided to evaluate them from firmware?

Best regards,

Keita

The one thing you can do easily is to look at the scaler values. If one channel counts all physical events, and you have all read out events, then the ratio give you the live/deadtime. The hardware scalers also keep running during the DRS readout.

Stefan

Thank you very much for your response.
Excuse me for my very stupid confirmation.
If I take N events finally and the hardware scaler value is M, the livetime is realtime*(N/M). Is this correct?

I would say not exactly, but it's a good approximation.

Thank you very much.

Hello, 

I made a modified version drs_exam_multi.cpp, but ran into an issue when running.  When I ran it, it only found the two boards with lower serial numbers (2781 and 2879) and complained that the others (2880 and 2881) were not v4. Would there be a simple workaround for this type of thing? Also, would I be able to use the .dat format to keep the file sizes down. 

If not, I am curious if there is a way I can at least set a default configuration for the drsosc program. It seems the drsosc.cfg is written when drsosc starts? Does it load the configuration from somewhere else? It would be very helpful to keep the same settings between runs, in particular the trigger delays, levels, trigger mode, and voltage offsets. Maybe I can even do this with just a few of the CLI commands? I know this is for experts only, but I think I would just need a few commands (setTrig, setTrigMode,  setTrigDelay, that sort of thing) if they do exist. I would check the help now, but I'm running, and I'm pretty sure I saw some for trigger settings. 

Anyhow, any help is appreciated in creating a more repeatable and automated data acquisition. Thanks!

Hi,

please note the the evaluation board is what it says, a board to evaluate the chip, and is not meant for a full-blown shiny multi-board DAQ channel, so support for that is kind of limited.

Strange that you only find two out of four boards. What happens if you disconnect the two boards the system finds and then try again? Might be that your USB hub does not have enough power to supply four boards (each taking 2.5W, so you need 10W in total). Unplugging some board will show you if you have a power problem.

The drsosc.cfg stores the current configuration. For this to work, the drsosc program has to have write access to the directory where the drsosc.cfg program is stored, which is usually the directory from where the program is started. Maybe you have to adjust permissions. Yes you have commands to set everything, just look into drs_exam.cpp and you will find most of them.

Best,
Stefan

Hi there,

Recently I bought a 5GSPS evaluation board with 2048 sampling points.
I want to read 4 inputs of the evaluation bord ar 5 GSPS or 2.5GSP and use an external trigger.
I've checked your website and download drs-5.0.5 which contains the source code in C. It seems that the file drs_exam.cpp can do what I am looking for.
So far I could make and compile the project in Linux Ubuntu, but I couldn't compile it in Windows 10.  I've used Cygwin64 to compile the project in windows 10.

I have the following questions:

1- Since I only need to compile the drs_exam.cpp file, could please help me with how can I compile it directly(without making the entire project). Or tell me which version of Wxwidget and libusb I have to install.

2- If you have any sample code that can read 4 inputs with an external trigger, please tell me where can I find it.

In the end, I want to write a wrapper on this C file(which returns digitized data) and run it from my python program. Thank you in advance.
Best regards,
Mehrpad

Sorry the late reply, I was on vacation. 

Here are some answers:

1. I'm sorry I can't help much here, since I currently don't have a Windows 10 computer here to compile any code. I moved now completely to MacOSX, being very similar to Linux. I'm not allowed to run a Windows 7 computer any more for security reasons. Last time this worked for me was with Wxwidget version 3.0 and libusb 1.0, but I guess libusb is not critical so you can use a newer version. If you just compile drs_exam.cpp, you don't need any Wxwidget library. That one is only used for the oscilloscope program.

2. The program drs_exam_2048.cpp is meant to read channels in 2048-bin mode.

3. To adjust the delay between the trigger and the readout, use the function b->SetTriggerDelayNs(xxx)

Best,
Stefan

Thank you for the reply.

In the version that I have, I cannot find drs_exam_2048.cpp file. Could you please send me the link to download the software folder, which contain this file.

Best,

Mehrpad

Hi,

I have been collecting some date using the DRS4 board at a trigger rate of 10-20 Hz,    I only need the timestamp and the amplitude, is there anyway to select only these two live as the data comes in to be stored. 

Alternatively,  What's the maximum file size or maximum number of events I can store in one binary file in linux. 

Thanks,

Best,

Abaz

The maximum file size depends on the underlying linux file system. Common values are 4-16 GBytes.

Stefan

Dear DRS4 team,

I'm experiencing some issues that seem to be isolated to the ASIC, and would like to understand if we are doing something wrong. There are several items to address in the post.

First, I do not think the noise observed is being injected from elsewhere on the board. If I run the DRS in transparent mode, the baseline noise is low, on order 3.5 mV (60 ADU), perhaps radiated from a clock. See below image. The scale is 0 to 1000 ADU with LSB = 6 uV (same AD9245 as eval board.). The DRS is in RUNNING state, I have forced a trigger in the ILA. This is for a single channel, CH0, 1024 cells.

In the next image, I show the waveform obtained from a full readout. This corresponds to ADC_READOUT state, and the plot uses the same 1000 ADU scale. Noise seems around 350 ADU now, many factors worse than before.

We've spent a lot of time trying to understand what's happening. One area that would be helpful to get some guidance on is the "t_samp" parameter. In Fig. 11 of the data sheet, should there be a t_samp label between t_s and t_clk? It just has arrows there with some width.

In our current firmware I believe R1 is simply one clock after R0 (for both ROI and full readout mode). Would this lead to the added noise observed in muxout?

This leads to the next question on what to actually use for t_samp. In the data sheet, page 4 "Timing Characteristics" it says to use t_samp = t0 + t_clk. Additionally, t0= 10 ns from that table. Fair enough.

But if I check this against the eval board timing, I see very different values. Here the clock is 15 MHz so t_clk=67 ns (I note another post about this topic https://elog.psi.ch/elogs/DRS4+Forum/713), so I expect t_samp = 77 ns. But in practice it looks like the R0 to R1 delay is ~465 ns? (cyan=RSRLOAD, yellow=SRCLK)

Given this, is t_samp a value that should be tuned by the user?

Best regards,

Sean

Dear Sean,

noise in transparent mode comes from some coupling to your system clock. But 3.5 mV RMS seems rather hight to me. You should get it to below 1 mV if the DRS4 input is clean (try to short it).

The noise in the readout is expected. It looks exactly as Plot3 from the data sheet. You have to calibrate it away with a fixed offset for each cell as described in this paper: https://arxiv.org/abs/1405.4975 (paragraph IV. A. Voltage Calibration).

Concerning t_samp: Fig 11 in the datasheet just tells you that the rising edge of the SRCLK should come later than t_s after the address change. t_s is the setup time and 5 ns. Fig 12 tells you that the ADC should sample the analog output of the DRS t_samp after the address change A0-A3 and t_samp after the rising edge of SRCLK. 

The digitizing speed of the evaluation board is indeed 15 MHz instead of the maximum 30 MHz, because this was easier to program in the FPGA. The t_samp has to be there so that the analog output signal of the DRS4 settles to its final value after each SRCLK pulse. If you sample "too early", you sample with the ADC the output when it is sill moving. So you have to wait until the analog is settled, but just before the next DRS sample becomes visible at the output. You can fine tune this with a differential probe at the DRS4 analog output (on a single ended probe you might drown in noise) on one channel of yoru scope and the ADC sample clock on the other channel of your scope. Note that the ADC sample clock cannot be derived straight from your FPGA clock, but you need some clock manager to fine-adjust its phase in 1ns steps.

But again, looking at your output, everything seems fine. You see the 5mV rms noise indicated in the datasheet table 1, which translates to about 20 mV peak-to-peak. If you do the offset calibration, this should go down to below 1 mV.

Best,
Stefan

Hi Stefan,

Thanks much for the quick reply. Ok, yes, things do seem ok after the offset calibration. I am running into some other issues I could use your advice on but will make a separate thread. As a preview, you can see hints in this waveform (periodic negative spikes).

 This one should be considered resolved.

If you do the cell calibration correctly, your noise should be ~0.4 mV. You seem to be 2-3x larger. The periodic negative spikes come if you dont' sample at the right time. Adjust t_samp until they are gone.

Stefan

Yes, there is some systematic board noise on this prototype, unfortunately 

Ok, then it seems the other post I made might still belong in this thread after all.

Thanks for confirming negative spike behavior, we now have a mitigation plan going forward.

Cheers,

Hi,

Is there a way that someone can help me and my student to enable RemoveSymmetricSpikes function in the drs_exam.cpp? We are not 100% sure how to call the function if you want to read out four waveforms.

Cheers,

Matthias

Just look at the definition of the function below, all parameters are explained there. In meantime we have a firmware fix to avoid the spikes inside the chip, but I have not yet found time to update the evaluation board.

Stefan

void DRSBoard::RemoveSymmetricSpikes(short **wf, int nwf,
                                     short diffThreshold, int spikeWidth,
                                     short maxPeakToPeak, short spikeVoltage,
                                     int nTimeRegionThreshold)
{
   // Remove a specific kind of spike on DRS4.
   // This spike has some features,
   //  - Common on all the channels on a chip
   //  - Constant heigh and width
   //  - Two spikes per channel
   //  - Symmetric to cell #0.
   //
   // This is not general purpose spike-removing function.
   // 
   // wf                   : Waveform data. cell#0 must be at bin0,
   //                        and number of bins must be kNumberOfBins.
   // nwf                  : Number of channels which "wf" holds.
   // diffThreshold        : Amplitude threshold to find peak
   // spikeWidth           : Width of spike
   // maxPeakToPeak        : When peak-to-peak is larger than this, the channel
   //                        is not used to find spikes.
   // spikeVoltage         : Amplitude of spikes. When it is 0, it is calculated in this function
   //                        from voltage difference from neighboring bins.
   // nTimeRegionThreshold : Requirement of number of time regions having spike at common position.
   //                        Total number of time regions is 2*"nwf".

Dear all,

I have a question about the function that drs4 can perform.

Is there any function in drs4 that is analogous to that of "persistence display" in oscilloscope?? (accumulating pulses)

Thank you

The chip itself can only sample a single waveform, that must be done in the attached software. The current DRSOscilloscope software coming with the evaluation board has not yet implemented that, but if you write your own software you can do so.

Are there plans to add the drs software to github? (asking because I have users @ethz.ch that want to use it on debian,
thus I'm creating official debian packages of it, if license allows so, but talking to upstream (the developers) would be
much easier on github (or irc) than on this "DRS4 Discussion Forum".

Best,

Not github, but bitbucket: https://bitbucket.org/ritt/drs4eb/src/master/

But development kind of stalled, so there will be updates only in case of severe bugs, which are kind of gone after 10 years now.

Best,
Stefan

> Are there plans to add the drs software to github? (asking because I have users @ethz.ch that want to use it on debian,
> thus I'm creating official debian packages of it, if license allows so, but talking to upstream (the developers) would be
> much easier on github (or irc) than on this "DRS4 Discussion Forum".
> 
> Best,