 Thu Jun 20 01:36:48 2019, Andrew Peck, Evaluation firmware wait_vdd state
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Dear Stefan,
I am working with others at UCLA on a custom made board built around the DRS4. We are in the process of writing firmware so I am adapting the
readout state machine from the evaluation board firmware. |
 Fri Jun 21 12:54:47 2019, Stefan Ritt, Evaluation firmware wait_vdd state
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Dear Andrew,
the posting you mention is still accurate. Any power supply will drop when you start the Domino wave, no matter how big your capacitor is. Unfortunately
the output signal of the DRS4 scales with VDD. So if your VDD drops by 40 mV and you get a trigger and you immediately start the readout, the output baseline |
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Mon Jun 24 23:07:35 2019, Andrew Peck, Evaluation firmware wait_vdd state
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Dear Stefan,
Thanks so much for clarifying this. We made wait_vdd a parameter controlled by software and will try to experiment with it to find some compromise
between deadtime and the offset added by the droop in VDD. |
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Fri Apr 12 09:39:30 2019, Lev Pavlov, multi-board
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Good afternoon, I use 5 boards in multi-mode, everything is connected according to the instructions. Can I measure the phase difference between
the two signals on channel 1 and channel 20? with each board the phase shift is added +16 ns I can not figure out how to compensate for this. give thanks |
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Fri Apr 12 09:55:50 2019, Stefan Ritt, multi-board
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Subtract 16 ns from your measured value ;-)
Stefan
Lev |
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Fri Apr 12 09:59:15 2019, Lev Pavlov, multi-board
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I understand this, thanks. But my Chief does not understand this, he wants to see the phase difference without “crutches”. And what
is meant in the manual 50 ps resolution? Maybe I just do not understand something? And if you submit a reference signal not in the mode of a garland, but |
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Fri Apr 12 12:50:18 2019, Stefan Ritt, multi-board
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If you have two signal going through two cables, the cable have never the same length (on a scale of picoseconds), and you have to calibrate that anyway.
So a proper timing calibration is not a crutch.
What do you mean by "manual 50ps"? The manual does not mention any resolution. In my experience, you can achieve about 10ps between |
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Thu Mar 14 03:43:49 2019, Deepak Samuel, How to buy DRS evaluation kit
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Dear Stefan,
I have emailed drs4@psi.ch a couple of times regarding the pricing of the evaluation kits for academic use in India and have not received any
reply and hence writing in this forum. Could you please help me in this? |
Fri Mar 8 19:35:11 2019, Abaz Kryemadhi, ROOT Macro for newest software 
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The older root macro did not work for me for data acquired with the newest software.
so for the newest software and multiple boards, I modified the read_binary.cpp into read_binary.C for those who like to use the root macro, see
the attachment. |
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Wed Mar 6 10:09:01 2019, Willy Chang, drscl "no board found" in some Win7 or Win8.X PCs
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Hi all,
When connecting the board and running the Zadig program, some Windows PCs may return "driver installation failed." I coudn't
find the solution from their download website. So I started the drscl first. Apparently it shows: Successfully scanned, but |
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Mon Feb 4 16:42:08 2019, Hans Steiger, Different Distances between the sampling points
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Dear All,
with the older software for my V5 Board i did not have the problem, that the distance between the sampling points (in time) is not the same (e.g.
a sampling point all 200ps for 5GS/s). |
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Mon Feb 4 16:46:04 2019, Stefan Ritt, Different Distances between the sampling points
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The sampling points are NOT equidestant, they have varying bin widths of 150ps to 250ps at 5GS/s. That's due the way the DRS4 chip works. You might
have neglected that fact in the past, but that would have led to poor timing resolutions (typically 1-2ns resolution only). To get bins with the same width,
you have to treat your waveform as a real X/Y points (or better U/T), and the re-sample that cure, maybe spline-interpolated, at 200ps bins. |
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Mon Feb 4 17:36:49 2019, Hans Steiger, Different Distances between the sampling points
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Sorry.... but is there a solution or a Root Macro, that reads the waveforms into a Root-Tree? I simply can not work anymore with the data.
Can you tell me, which software was in use in early 2017?
All the best, |
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Mon Feb 4 18:18:22 2019, Stefan Ritt, Different Distances between the sampling points
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elog:361
Hans
Steiger wrote:
Sorry.... but is there a solution or a Root Macro, that reads the |
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Sat Feb 2 00:13:12 2019, Hans Steiger, Saving Rate (only 15Acq/s)
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Dear All,
when I use my Evaluation Board with some PMTs I can digitize 450 Acq/s or so. But when I want to save the waveforms the rate goes down. The Acqu. |
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Sat Feb 2 10:10:22 2019, Stefan Ritt, Saving Rate (only 15Acq/s)
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The reduction of rate is because you save in XML format, which is an ASCII format, so human readable, but takes long to write. If you switch to binary
format and write on a decent fast hard disk, you should get back to 450 Acq/s.
Stefan |
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Tue Jan 29 14:43:44 2019, Abaz Kryemadhi, ROOT Macro for data acquired with the newest software
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Hello,
Is there a root macro for decoding binary data acquired with the newest software for single board or multi-boards daisy chained?
Cheers, |
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Wed Jan 30 17:08:58 2019, Stefan Ritt, ROOT Macro for data acquired with the newest software
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This one elog:361 should still work.
Stefan
Abaz |
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Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study
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We have been using DRS4 IC in our design for quite some time and it is giving good performance.
Till now we were using Domino wave frequency as 1 GSPS by use of reference clock to DRS4 and internal PLL of DRS4. Recently we tried to use 4GSPS
by modifying the reference clock. |
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Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study
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The Domino wave is most stable at 5 GSPS, slowly degrades down to 3-2 GSPS, and at 1GSPS gets some significant jitter. This is for internal reasons in
the chip and cannot be compensated by the loop filter. It is therefore important to run it as fast as possible if you want to achieve best timing resolution.
As a rule of thumb, the jitter at 5 GSPS is about 20-25 ps, and at 1 GSPS it is maybe 150 ps. If you require good timing resolution, you can use the 9th |
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Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue
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Hi,
We are using the DRS4 Evaluation Board as a digitizer in our laboratory.
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Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue
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That's not a bug, but a feature of the DRS4 chip. The time bins have different values by the properties of the chip. They are generated by a chain of inverters,
which all have different propagation times. This delay is measured by the time calibration and then applied. If you want equidistant bins,
you have to interpolate your data points (linearly or by splines) and resample the signal. You can find more details in the DRS4 data sheet.
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Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue
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Thanks a lot for the quick response.
We will do as you suggest.
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Mon Nov 5 17:17:08 2018, Sean Quinn, Pi attenuator on eval board inputs?
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Dear DRS4 team,
I am curious about this part of the circuit: |
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Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs?
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The attenuator compensates for the gain of the buffer which is slightly above one. In addition, it serves as a "placeholder" in case one wants
larger input signals. One can easily convert the attenuator to -6db, -12db, etc. by chaning the resistors.
Stefan |
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Thu May 17 13:29:34 2018, Stefan Ritt, "Symmetric spikes" fixed
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Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.
The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel,
symmetric around sampling cell #512. See first attachment. |
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Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed
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Hi,
Is it possible to fix it by FPGA changes? I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly
put this three commands. Could you please attach app.vhd file for eval board with example how to fix ? |
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Tue Sep 4 13:04:30 2018, Stefan Ritt, "Symmetric spikes" fixed
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Yes it's possible, but I have to find time for that. The software of the evaluation board takes care of the spikes ("remove spikes"), so
I thought it's not so urgent to fix that in the FPGA (which takes me some time).
Stefan |
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Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed
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Ok, so I made it ... and Yes it works :),
https://youtu.be/0noy4CoFoh8
here is changed part in drs4_eval4_app.vhd |
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Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed
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Dear DRS4 team,
On page 3 of the data sheet, Table 1. for readout speed a typical value of 10 MHz is specified, but in the comment column it notes optimal performance
achieved at 33 MHz. |
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Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed
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The analog output of the DRS4 chip needs some time to settle. In principle it need an infinite amout of time (exponential curve) to settle to 100% of
the final value. So if we sample after a finite time, there is some error we do. Some of the error will be taken care of the voltage calibration, but there
remains some residual error depending on the value of the previous sampling cell. So all sampling speeds 10 MHz, 16 MHz, 33 MHz are kind of rule of thumbs. |
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Mon Aug 13 19:44:59 2018, Martin Petriska, Latch delay support
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Hi,
https://forge.physik.rwth-aachen.de/projects/drs4-rwth
Not sure about their licensing, but is it possible to add latch delay support to official firmware ? |
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Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support
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I put that on the wish list, but I won't have time for that in the next months.
Stefan
Martin |
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Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing
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Using a test pulse split into two channels of the DRS4 Evaluation Board v5, I looked at the time resolution using a leading edge threshold.
The voltage and timing calibration was performed. One method (1) is to linearly interpolate between two points of the raw waveform that
is above and below the threshold (this is exactly the algorithm given in read_binary.c in the drs4 source distribution); and another (2) is to |
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Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing
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Just a follow-up update.
It turns out that I was using a cubic spline interpolation with smoothing. If I required the cubic spline to go through the sampled points, then
I obtained similar time resolution as the simple linear interpolation. |
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Thu Jun 28 19:55:45 2018, Woon-Seng Choong, Negative Bin Width
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I am using a DRS4 Evaluation Board v5 and running the drsosc.exe version 5.06 on a Window 7 machine. I have performed the voltage and timing calibration.
With test pulses on channel 1 and 2, I collected binary data file with all 4 channels active sampling at 5GSPS.
Attached is a distribution of the bin_width vs. cell # for all the 4 channels. Note that there are few cells with bin_width < 10 ps. |
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Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width
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Yes that's normal. A negative cell bin width means that the next cell N+1 samples the input signal before cell N. This can happen due to the signal
routing on the DRS4 chip.
Stefan |
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Tue Jun 19 06:42:23 2018, Phan Van Chuan, The data acquisition speed
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Dear Stefan,
We are using an DRS4 board V5.1 for building a metering system for the scintillator detector by a Labview program. The program was built based
on the functions in DRS.cpp and it reads data from channel 0 very well (Fig 1). Now, I am having a problem with the data acquisition from DRS4 board. The |
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Tue Jun 19 10:05:50 2018, Stefan Ritt, The data acquisition speed
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How do you tigger the board? In your code below you start the board (StartDomino()) and then wait for a trigger. Setting the trigger level to zero (via
SetTriggerLevel(0)) is certainly wrong. Please have a look at drs_exam.cpp in the distribution and use the same functions used there. If you want to trigger
the board, you need some external pulser with high enough rate (more than 500 Hz or course). You can also "software" trigger the board with a |
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Tue Jun 19 12:54:51 2018, Phan Van Chuan, The data acquisition speed
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Thank Stefan Ritt, I added the SoftTrigger() just after StartDomino(), so now, The data acquisition speed the same speed as in the DRS oscilloscope.
I have misunderstood the "auto" trigger on an oscilloscope as setting SetTriggerLevel (0).
Thank so much! |
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Wed Jun 13 13:23:17 2018, Julian Kemp, Maximum analog input voltage
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Dear all,
I have been wondering what the maximum analog input voltage for the DRS4 V5 evaluation board is. It came with a sticker indicating that it is
"2.5V pk Max". On the other hand, when checking the manual (https://www.psi.ch/drs/DocumentationEN/manual_rev50.pdf), it says maximum allowed |
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Wed Jun 13 13:42:47 2018, Stefan Ritt, Maximum analog input voltage
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In principle the numbers in the manual are correct. But they relate to pulses of a certain length, because the input protection only works for DC voltage
and for pulses which are not too long. Since we could not write this all on the label of the board, we decided to put there 100% safe value as a "warning"
to people, meaning that if pulses are above 2.5V, they should look into the manual and read the details. |
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Wed Jun 13 16:34:28 2018, Julian Kemp, Maximum analog input voltage
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Thank you! That solves my problem.
Stefan
Ritt wrote:
In principle the numbers in the manual are correct. But they relate |
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Thu Jun 7 16:27:21 2018, Phan Van Chuan,
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Dear Stefan,
I am using an DRS4 board to test the signal from an scintillator detector; It has connected well to the computer on DRS Oscilloscope (Figure
1). Now, I am having a problem of developing from the code of the drs_exam program, because the DRS4 board has not connected to the computer when translation |
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Fri Jun 8 08:11:05 2018, Stefan Ritt,
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Several people reported this problem, but we cannot reproduce it at our lab. Both the oscilloscope and the command line interface use exactly the same
code to connect to the board. Have you tried the solution reported here: elog:657 ?
Best, |
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Tue Feb 27 13:17:00 2018, Steven Block, WIndows Connection problem with drs507 SOLVED
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Hello All,
I too have been struggling with trying to get the drs4 (507) to work on my windows machine and I found it to be a problem with the libusb library.
My solution is as follows and has worked on multiple PC's. I ran this solution after I first plugged in the drs4 and installed 507. |
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Tue Feb 27 13:29:47 2018, Stefan Ritt, WIndows Connection problem with drs507 SOLVED
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Dear Steven, many thanks for this information, this is very useful. I know of people having problems on Windows 10, maybe this will also help them.
Stefan
Steven |
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Wed May 9 14:07:10 2018, Alec Shackleford, WIndows Connection problem with drs507 SOLVED
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Thank you for this fantastic solution. I had almost reinstalled windows 7 to see if that would solve the issue!
All the best, |
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Mon May 14 09:21:29 2018, Alessio Berti, WIndows Connection problem with drs507 SOLVED
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Hi,
I have a machine with Windows 10 and the solution provided by Steven works fine. To give more details, the driver installed in my case is WinUSB
(i.e. libusb, v6.1.7600.16385). |