 Thu Mar 31 19:30:26 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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I would like to be able to trigger in this fashon: channel 0 > 0.1 and. channel 1< -0.1, because I have a positive and a negative signal.
Can DRS4 (5) Eval board do this kind of trigger?
Thanks! |
 Thu Mar 31 19:35:06 2016, Stefan Ritt, Trigger on the And of a positive and negative signal
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No. You have to use an inverter for one of your signals.
Stefan
Abaz |
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Thu Mar 31 19:44:38 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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Ok, thanks! do you know an easy in-line inverter like mini-circuit or digikey? Can also redesign the detector I gues to produce
positive signals, just it might be easier if there was a simple inverter if you are aware of? thanks Abaz
Stefan |
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Thu Mar 31 20:34:25 2016, Stefan Ritt, Trigger on the And of a positive and negative signal
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Here is one (SI 100): https://www.picoquant.com/products/category/accessories/adapters-splitters-cables-various-accessories-for-photon-counting-setups
Abaz
Kryemadhi wrote:
Ok, thanks! do you know an easy in-line inverter like mini-circuit |
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Thu Mar 31 20:38:05 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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Thanks, that looks just fine.
Stefan
Ritt wrote:
Here is one (SI 100): https://www.picoquant.com/products/category/accessories/adapters-splitters-cables-various-accessories-for-photon-counting-setups |
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Thu Mar 31 20:48:00 2016, Chris Thompson, Trigger on the And of a positive and negative signal
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I needed a fast pulse inverter in order to feed signals from the recent SensL SiPMs into a conventional CFD which only accepted negative signals. I got
a very small ferite torridal transformer from Coilcraft and wired up to invert signals then inserted into in 50 ohm coax cable and it works fine. These
things cost only a few cents each! |
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Fri Apr 1 01:30:40 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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Hi Chris,
I am looking at Sensl SiPMs as well, can you send the part number from Coilcraft?
Thanks! |
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Fri Apr 1 22:09:07 2016, Chris Thompson, Trigger on the And of a positive and negative signal
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The coilcraft part number is: JA4220-ALB. Iordered two of them and they were sent as free samples. You might want to buy some slightly bigger
ones. I found them so small it was very hard to solder the coax cable to the connectors. Since I got them, I managed to damage one as they are quite fragile!
In the confirmation email I got there was some contact info which may be useful for you: "For help, contact Victoria Berner |
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Sat Apr 2 17:22:34 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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Thanks again, this is very useful, just another question did you put any other passive elements in the circuit for inverting the signal
or just simply swaped the transformer connections?
Chris |
Sun Apr 3 22:10:19 2016, Chris Thompson, Trigger on the And of a positive and negative signal 
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No there are no other components. I put a photo of the inverter with its cables SMA and one end, BNC at the other. You can see it is very small. I glued
the inverter to a piece of thin plywood, and fixed the cables to it before attempting to solder them to the pads on the ferite bead support
Abaz |
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Sun Apr 3 22:34:28 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal
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Thanks, great!
Chris
Thompson wrote:
No there are no other components. I put a photo of the inverter |
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Sat Apr 2 11:21:10 2016, Felix Bachmair, Question about timimng calibration
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Hi,
I am trying to understand some details about the timing calibration.
We wrote our own code but we more or less use the ideas of the Oscilloscope class. |
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Sat Apr 2 11:41:07 2016, Stefan Ritt, Question about timimng calibration
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The evaluation board normally has 1024 bins per channel. We offer an option with 2048 bins using channel cascading, to capture longer waveform windows.
The binary data format is however defined as having 1024 bins. Therefore, for the 2048 bin boards, the software averages over two adjacent cells and saves
effectively 1024 bins. The noise of each bin improves this way by sqrt(2). The time however is not very well defined, since you average the voltage of |
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Fri Mar 11 19:50:18 2016, Dominik Neise,
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Hello Stefan,
I just stumbled again over a phrase in the DRS4 datasheet I never really understood, but didn't find the time to ask.
On page 8 it says: "An internal circuit ensures that the write signal is always 16 cells wide." |
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Tue Mar 22 12:54:41 2016, Stefan Ritt,
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Yes this is correct. But it is a sample-and-hold circuit. So the sampling cell follows the input for 3.2 ns, then samples and holds the current value
at the end of the period.
Dominik |
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Mon Feb 29 12:58:17 2016, Dmitry Philippov, baseline shift
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Hello! My name is Dmitry. I am from SiPM Lab is NRNU MEPhI (Russia, Moscow). We bought DRS4 evaluation board V5 with firmware 21305. We use 5.0.4 build
21911 2015-11-23 software version (and before that we used 5.0.3 build 21508, 2014-10-15) with Windows 7 32bit.
We observe some strange behaviour. When we save waveforms (in xml or binary data) we see that some of them have the baseline shifted of about |
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Mon Feb 29 13:09:29 2016, Stefan Ritt, baseline shift
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The baseline shift comes from some instable power supply inside the evaluation board which cannot be controlled to the mV level. In a real measurement,
you usually get an additional baseline shift due to some environmental electromagnetic interferences, such as a 50 Hz signal. People fix this shifting
baseline by always aquiring a small portion (10-20 samples) of the baseline before any signal from a particle detector. The signal is then corrected event-by-event |
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Thu Nov 26 18:59:27 2015, Robert Adams, Saving histogram data
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I would really love to be able to save histogram data, though I have not been able to do this. I could take a screenshot and extract the data from an
image, but would prefer to avoid this if there is a simpler way... possibly I have overlooked something obvious? Thanks very much for any advice or tips. |
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Tue Feb 16 11:21:43 2016, Stefan Ritt, Saving histogram data
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There is no histogram save functoinality in ther DRSOscilloscope program - on purpose. The board and the software are meant to evaluate the board, not
to replace a full DAQ system. If we want to save histograms, you maybe also want to set the range, make cuts, do fits etc. So it would take lots of resources
to add all that. Therefore we recommend to use the stand-alone C program drs_exam.cpp to read the board, the you can either do whatever you want in the |
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Tue Feb 16 11:55:54 2016, Martin Petriska, Saving histogram data
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Robert
Adams wrote:
I would really love to be able to save histogram data, though I have |
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Thu Jan 14 21:49:37 2016, Chris Thompson, Triggering of DRS4 in the fastest sampling mode
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I am attempting to use the DRS4 to measure the timing resolution of a pair of SensL silicon photomultipliers (SiPM). In order to do this I need to trigger
the DRS4 only when there is a coincidence between the two input signals, and hopefully make histograms of the relative detection times of each detector.
There are two completely separate issues. (1) I think this may just be a labelling error. In the first image (OR_mode_selected) one can clearly |
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Fri Jan 15 08:09:00 2016, Stefan Ritt, Triggering of DRS4 in the fastest sampling mode
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Hi Chris,
if you ever used an oscilloscope, you might be familar with the button controlling the riger in respect to "risign edge" vs. "falling
edge". I copied the same for the DRS software. So just click on that button: |
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Wed Dec 23 15:38:14 2015, mony orbach, Dtap stops toggling after 40msec
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Hi
the drs4 start to generate Dtap signal after reset and standard configuration.
while in reset Denable and Dwrite are low |
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Wed Dec 23 15:48:42 2015, Stefan Ritt, Dtap stops toggling after 40msec
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No idea what you do wrong. I need to see oscilloscope traces for all your inputs and voltages. What is your REFCLK input?
mony
orbach wrote:
Hi |
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Thu Dec 24 10:51:31 2015, mony orbach, Dtap stops toggling after 40msec
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my refclk is 1.25Mhz
what are the inputs and voltage you need to see?
Avdd and Dvdd are 2.5v |
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Thu Dec 24 12:45:41 2015, Stefan Ritt, Dtap stops toggling after 40msec
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I want to see the trace on the scope for the DTAP, the REFCLK, the DENABLE and the DWRITE.
Probably (but it's just a guess), you have a problem with the soldering of the DRS chip, maybe to the PLL loop filter. Or you chose the wrong
capacitor/resistor combination for the loop filter. There are ~10 other groupsl who did the same and it works for all of them, so there must be a problem |
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Sun Dec 27 15:41:32 2015, mony orbach, Dtap stops toggling after 40msec
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Hi
We have some measures to show (attached)
Dtap and Denable
Dtap+Denable in zoom
Dtap + Refck+
Dtap + Dspeed
From the screen |
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Mon Dec 28 11:05:15 2015, Stefan Ritt, Dtap stops toggling after 40msec
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Thanks for posting the plots. It really looks like the PLL is not working. I see two possible reasons: 1) The PLLEN bit in the configuration register
is not set and 2) The REFCLK signal does not reach the chip. We had cases whrere people had a hard time to solder the DRS4 correctly due to the small pins.
So if the REFCLK+ and REFCLK- signals have a poor connection, then the PLL of course won't work. Putting some more tin at the pins manually usually |
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Mon Dec 28 11:21:54 2015, mony orbach, Dtap stops toggling after 40msec
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Hi Stefan
Thanks for your input.
We are in the process of assemble another PCB board. |
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Wed Dec 30 16:25:35 2015, mony orbach, Dtap stops toggling after 40msec
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Hi
We have resolve the problem, the Dtap is now working correctly.
There were two problems: |
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Wed Dec 30 17:00:00 2015, Stefan Ritt, Dtap stops toggling after 40msec
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While I can understand 1., I'm puzzeled by 2.
If you put the chip in standby mode, the internal current sources are switched off, which of course make the domino wave non-functional. This
is clearly stated in the data sheet. |
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Thu Jan 14 14:00:26 2016, mony orbach, Dtap stops toggling after 40msec
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surrey i forgot to update..
after carefully examining our VHDL we found out that there are brief times that we put A0-A3 in 1111
after making shore that a0-a3 never get 1111 value thae drs4 woks as expected. |
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Thu Jan 14 14:11:06 2016, Stefan Ritt, Dtap stops toggling after 40msec
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Thanks for the update, I will add a note into the data sheet.
mony
orbach wrote:
surrey i forgot to update.. |
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Tue Jan 12 17:57:03 2016, Jack Bargemann, Compiling DRS-exam
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I am trying to compile drs-exam, but am getting an error message I do not understand:
1>musbstd.obj : error LNK2019: unresolved external symbol _usb_open referenced in function _musb_open
1>musbstd.obj : error LNK2019: unresolved external symbol _usb_close referenced in function _musb_close |
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Tue Jan 12 21:02:31 2016, Stefan Ritt, Compiling DRS-exam
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I guess you are compiling under MS Windows ??? You probably don't link correctly to the USB lib. Try to compile the examples coming with libusb-1.0
to make you everything is right there.
Jack |
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Wed Jan 6 15:51:58 2016, Larry Byars, Use of Channel Cascading in drs_exam.cpp
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Hello Stefan,
Here in Rockford, TN we just got a new DRS4 evaluation board (Serail # 2612, Board Type 9, Firmware 21305) which is labeled as combined 2048.
It looks like the drs_exam.cpp only works with 1024 samples per channel. We'd like to be able to get 2048 samples from each of the four channels |
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Tue Jan 12 15:42:31 2016, Larry Byars, Use of Channel Cascading in drs_exam.cpp
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An update. I have been successful in making modifications to drs_exam.cpp so that I can get 2048 samples per channel.. The main changes were to the size
of the time_array and wave_array and adding a call to Set ChannelConfig(0,8,4). It was also necessary to change the parameters to GetWave so that the Trigger
Cell and WSR values were passed to get the channel combinations correct (2048 channel.ppt). |
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Tue Jan 12 16:06:07 2016, Stefan Ritt, Use of Channel Cascading in drs_exam.cpp
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Hi Larry,
sorry my late reply, swamped with work here. You were right in the modifictions you did, congrats. The speed limitation of 500 events come from
USB2, which simply is not fast enough. The 500 Hz are mentioned on the evaluation board web site, so you should have seen that before ordering. Some people |
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Wed Nov 25 02:52:35 2015, Chris Thompson, PC software beyond Windows 7
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I am new to this forum. I have ordered a DRS4 evaluation board for doing experiments with very fast PET detectors. It has not arrived yet. The version
of the manual I downloaded today shows software installation instructions for Windows 7 and earlier versions. I intend to use it on a 64bit PC running
Windows 8.1. Will the Windows 7 driver work, or is there an updated version for Windows 8 or 10? |
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Wed Nov 25 08:20:47 2015, Stefan Ritt, PC software beyond Windows 7
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Have a look here elog:434
Chris
Thompson wrote:
I am new to this forum. I have ordered a DRS4 evaluation board for |
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Wed Nov 25 17:36:25 2015, Chris Thompson, PC software beyond Windows 7
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I tried this suggestion of changing the startup settings to ingore driver license signing (as suggested in the post # 434), but when I tried to install
the software I got a error message which I captured from the screen and I have attached. Perhaps I have the wrong version, or, as suggested, the file I
downloaded from your site is incomplete? |
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Sat Dec 5 02:39:20 2015, Chris Thompson, PC software beyond Windows 7
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I tried restarting Windows 10 in a way the allowed me to use "advanced startup options" Option 7 suggested it was to restart without mandatory
driver signing. However, the error persists. Has anyone tested this latest version 5.0.4 on Windows 10? My hardware arrived today, and I am anxious to
test it.!!!! |
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Sat Dec 5 03:21:21 2015, Chris Thompson, PC software beyond Windows 7
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On a hunch, I tried downloading V 5.0.3 instead. This works, and I now have the oscilloscope mode displaying signals! (just to make sure, I re-tire version
5.0.4 and still get the same error. So, in summary V 5.0.3 seems to install successfully and work with Windows 10, but the newer V5.0.4 does not install...
I assmume that I am missing something though, as the newer version is 10 Mbytes bigger! |
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Tue Jan 12 12:57:46 2016, Stefan Ritt, PC software beyond Windows 7
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The 5.0.4 version was corrupt on our server. I fixed it, so now it shoudl also work fine (although there are only very minor changes between 5.0.3 and
5.0.4).
/Stefan |
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Tue Nov 3 22:37:56 2015, Will Flanagan, Latest macro for DRS4 V5
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Hi DRS4 Experts,
I have an extremely naive question: Is there any official macro to unpack the DRS4 binary files? All I am looking to do is to plot a few of my
waveforms and manipulate them in root. I am using OSX 10.10 and ROOT 5.34. |
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Tue Nov 3 23:15:38 2015, Will Flanagan, Latest macro for DRS4 V5
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I should of course mention that I looked through the DRS4 website and didn't see anything obvious: https://www.psi.ch/drs/evaluation-board
Thanks,
Will |
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Wed Nov 4 15:40:10 2015, Stefan Ritt, Latest macro for DRS4 V5
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Have a look here: elog:361
Will |
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Thu Nov 5 00:18:42 2015, Will Flanagan, Latest macro for DRS4 V5
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Hi Stefan,
This is absolutely perfect.
Thanks, |
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Wed Oct 7 13:06:34 2015, Ilja Bekman, Voltage Calibration with signal on the input
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Wed Aug 19 15:07:53 2015, Martin Petriska, QtPALS
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There is software for DRS4 board and positron lifetime measurement availiable. Still in beta but works. Its usable for measuring time between
pulses in two or three channels and histogramming that time. (May be time of flight measurement should be tested too) Project code is here: http://sourceforge.net/projects/qtpals/.
More about it is here http://iopscience.iop.org/1742-6596/505/1/012044/. |
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Fri Aug 7 18:41:37 2015, dante, DRS4
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Hi
I have just installed DRS4, but when I try to view it from the USB it don't work. Why?
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Fri Aug 7 20:32:15 2015, Felix Bachmair, DRS4
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Hi
Did you copy the udev rule 41-drs.rules into /etc/udev/rules.d/ ?
Which operating system are you using? |
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Mon Jul 20 09:25:38 2015, Chenfei Yang, Measure the time between different samples
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Hi,
I have a question using a data acquisition card base on DRS4 chip. How can I measure the time between several samples of one channel，with the
accuracy of like nanoseconds , for I am using the internal trigger. Is there any complete work about this problem？
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Thu Jul 23 13:46:12 2015, Stefan Ritt, Measure the time between different samples
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> Hi,
> I have a question using a data acquisition card base on DRS4 chip. How can I measure the time between several samples of one channel，with the
accuracy of like nanoseconds , for I am using the internal trigger. Is there any complete work about this problem？
|
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Thu Jul 2 13:20:51 2015, Felix Bachmair, Creation of Object files
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HI,
We are using the DRS4 Board in the EUDAQ framework [1]. We wrote a a Producer based on the software of the evaluation board, which is using the
DRS class/header/src files. |
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Fri Jul 3 17:13:27 2015, Stefan Ritt, Creation of Object files
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Hi Felix,
the distribution does not contain any binaries, since there are too many Linux distributions around, so everybody compiles from the sources under
Linux. Do you want me to just add libDRS.so to the official Makefile? Actually you are the first one asking for this. Would it be beneficial to have this |
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Mon Jul 6 11:30:56 2015, Felix Bachmair, Creation of Object files
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Hi Stefan,
That's fine for me. I thought it might be interesting for others as well..
Cheers |
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Mon Jul 6 19:25:27 2015, Stefan Ritt, Creation of Object files
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Anyhow it would be nice if you just post your Makefile here, which runs with the standard distribution, so people can use it if needed.
Stefan
Felix |
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Tue Jul 7 09:29:21 2015, Felix Bachmair, Creation of Object files
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Yes of course no problem.
You can download via github https://github.com/veloxid/DRS4-v5-shared and I
also put it in the attachment. |
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Sat May 23 11:03:20 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz
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Hi
We are working with the DRS 4 V5 version and we investigated an issue with the trigger at rates below ~120 Hz.
As long as we have a trigger rate of more than 125 Hz. everything seems to work fine and we are recording more or less all events. |
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Thu Jul 2 08:53:17 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz
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Hi,
We did a further investigation of this problem:
We figured out that this issue seems to be related to the kernel. |
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Thu Jun 18 17:33:05 2015, Gregor Kramberger, drs 5.03 and windows 8.1
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I have problems with driver installation on windows 8.1 (software version 5.03). I have sen that that has been an issue before (driver signing)
and I would like to know if this has been solved. We run several DRS4 evaluation boards on different PCs all running Win7 without any problems.
Therefore we are almost confident that it is related to Win 8.1. Thanks. |
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Fri Jun 19 12:32:10 2015, Gregor Kramberger, drs 5.03 and windows 8.1
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Gregor Kramberger wrote:
I have problems with driver |
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Tue Jun 16 20:45:54 2015, Michael Buadelk, DRS4 Evaluation Board Osc Application
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Hi, I have a DRS4 v5 evaluation board and I have a novice question about the oscilliscop application. When I connect it to a photo-detector (silicon
photo-multiplier to be exact), the signal appears only on one half of the screen, and I cannot change it to be full screen, and pulse to be centered. I
tried changing delay time and played around with the settings of the applicaton but no success. I'd apprecite if someone help me on this, probably |
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Tue Jun 16 22:26:41 2015, Stefan Ritt, DRS4 Evaluation Board Osc Application
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There is a horizontal position slider in the "Horizontal" box on the right side below the trigger delay. Use it.
Michael
Buadelk wrote:
Hi, I have a DRS4 v5 evaluation board and I have a novice question |
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Tue May 19 14:14:45 2015, Ilja Bekman, DRS4 firmware UCF constraints
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Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.
I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that
|
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Fri May 22 14:25:45 2015, Stefan Ritt, DRS4 firmware UCF constraints
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> Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.
>
> I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that
|
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Tue May 26 11:27:27 2015, Felix Bachmair, DRS4 firmware UCF constraints
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> > Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.
> >
> > I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that
|
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Fri Jun 5 12:07:38 2015, Stefan Ritt, DRS4 firmware UCF constraints
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I presume you have several evaluation boards and want to run them in sync, right?
This can be either made in daisy-chain mode (see manual page 25). In this case only the master board can trigger the slave boards. If you need to trigger |
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Fri Jun 5 13:15:35 2015, Felix Bachmair, DRS4 firmware UCF constraints
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Hi Stefan,
No we only use one evaluation board. We use the evaluation board as a part of our beam test setup. It includes a telescope based on the current PSI46V2.1
CMS Pixel chip and a trigger logic board for triggering the telescope and the evaluation board. This includes a
|
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Fri Jun 5 13:29:55 2015, Stefan Ritt, DRS4 firmware UCF constraints
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Do the following:
Use the TRG OUT of the evaluation board as a "busy". Only if this signal goes low (meaning that the readout of the board is complete and the board has |
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Fri Jun 5 13:32:03 2015, Stefan Ritt, DRS4 firmware UCF constraints
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Actually we should take this offline not to pester other DRS users which are not interested in this topic. Please call me directly (3728) at PSI.
/Stefan |