DRS4 Forum
  DRS4 Discussion Forum, Page 9 of 15  Not logged in ELOG logo
Entry  Tue May 19 14:14:45 2015, Ilja Bekman, DRS4 firmware UCF constraints  
    Reply  Fri May 22 14:25:45 2015, Stefan Ritt, DRS4 firmware UCF constraints  firmware.zip
       Reply  Tue May 26 11:27:27 2015, Felix Bachmair, DRS4 firmware UCF constraints  
          Reply  Fri Jun 5 12:07:38 2015, Stefan Ritt, DRS4 firmware UCF constraints  
             Reply  Fri Jun 5 13:15:35 2015, Felix Bachmair, DRS4 firmware UCF constraints  
                Reply  Fri Jun 5 13:29:55 2015, Stefan Ritt, DRS4 firmware UCF constraints  
                   Reply  Fri Jun 5 13:32:03 2015, Stefan Ritt, DRS4 firmware UCF constraints  
Entry  Sun May 24 09:34:27 2015, Peter Steinberg, Peculiar behavior of time values for Rev5 DRS4 EB 
    Reply  Wed Jun 3 09:07:38 2015, Stefan Ritt, Peculiar behavior of time values for Rev5 DRS4 EB 
Entry  Wed May 13 09:31:18 2015, Chenfei Yang, transparent-mode voltage tek00000_.png
    Reply  Wed May 13 09:45:51 2015, Stefan Ritt, transparent-mode voltage 
       Reply  Wed May 13 09:55:09 2015, Chenfei Yang, transparent-mode voltage 
          Reply  Wed May 13 10:16:40 2015, Stefan Ritt, transparent-mode voltage 
             Reply  Wed May 13 10:27:43 2015, Chenfei Yang, transparent-mode voltage 
             Reply  Wed May 13 12:34:49 2015, Stefan Ritt, transparent-mode voltage 
                Reply  Wed May 13 12:52:22 2015, Chenfei Yang, transparent-mode voltage 
                Reply  Wed May 13 16:13:07 2015, Chenfei Yang, transparent-mode voltage 
                   Reply  Wed May 13 16:25:24 2015, Stefan Ritt, transparent-mode voltage 
Entry  Wed May 13 00:52:51 2015, Cosmin Deaconu, Getting Trigger Source 
    Reply  Wed May 13 08:19:53 2015, Stefan Ritt, Getting Trigger Source 
Entry  Wed May 13 01:07:36 2015, Cosmin Deaconu, DRS4 Evaluation Board + Powered USB Hub 
Entry  Sun Apr 5 22:16:48 2015, Julien Wulf, DRS4 Evaluation Board Baseline/Voltage Calibration  
    Reply  Tue Apr 21 12:52:18 2015, Stefan Ritt, DRS4 Evaluation Board Baseline/Voltage Calibration  
       Reply  Tue Apr 21 13:03:38 2015, Daniel Stricker-Shaver, DRS4 Evaluation Board Baseline/Voltage Calibration  
          Reply  Tue Apr 21 13:06:39 2015, Stefan Ritt, DRS4 Evaluation Board Baseline/Voltage Calibration  
Entry  Thu Apr 9 11:46:33 2015, Felix Bachmair, DRSBoard::SetTriggerSource 
    Reply  Tue Apr 21 12:01:45 2015, Stefan Ritt, DRSBoard::SetTriggerSource 
Entry  Wed Oct 15 10:14:32 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
    Reply  Wed Oct 15 10:52:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ 
       Reply  Wed Oct 15 11:34:43 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
       Reply  Wed Oct 15 12:15:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ drs_exam_multi.cpp
          Reply  Fri Apr 17 10:07:38 2015, Simon Weingarten, Clock settings in daisy chain DAQ 
             Reply  Mon Apr 20 13:08:24 2015, Stefan Ritt, Clock settings in daisy chain DAQ 
Entry  Mon Mar 16 16:07:39 2015, Hermann-Josef Mathes, Running 2 instances of a DRS DAQ program 
    Reply  Tue Mar 17 02:53:26 2015, Stefan Ritt, Running 2 instances of a DRS DAQ program 
       Reply  Thu Mar 19 07:37:52 2015, Daniel Stricker-Shaver, Running 2 instances of a DRS DAQ program 
Entry  Fri Feb 13 10:12:16 2015, Andrzej Grzeszczuk, drs4 and root 
Entry  Fri Jan 16 13:29:05 2015, Rainer Hentges, Mac OSX Yosemite 10.10 
    Reply  Fri Jan 16 14:12:19 2015, Stefan Ritt, Mac OSX Yosemite 10.10 
Entry  Mon Nov 17 16:36:18 2014, Mickey Chiu, Raspberry Pi drsosc does not exit properly 
    Reply  Tue Nov 25 14:06:34 2014, Stefan Ritt, Raspberry Pi drsosc does not exit properly 
Entry  Sun Oct 19 14:36:54 2014, Chris Tully, coverting the xml file format into binary 
Entry  Wed Aug 13 20:17:19 2014, Roman Gredig, binary files time calibration header in drs-5.0.2 
    Reply  Thu Oct 16 16:16:12 2014, Stefan Ritt, binary files time calibration header in drs-5.0.2 
Entry  Tue Aug 26 14:16:26 2014, Roman Gredig, binary files with more than 4 drs board ver. 5.0.2 
    Reply  Thu Oct 16 16:15:16 2014, Stefan Ritt, binary files with more than 4 drs board ver. 5.0.2 
Entry  Tue Oct 7 14:09:02 2014, Stephane Debieux, USB Microcontroller firmware 
    Reply  Mon Oct 13 16:46:56 2014, Stefan Ritt, USB Microcontroller firmware 
       Reply  Mon Oct 13 17:08:40 2014, Stephane Debieux, USB Microcontroller firmware 
          Reply  Mon Oct 13 17:14:58 2014, Stefan Ritt, USB Microcontroller firmware 
             Reply  Tue Oct 14 16:21:07 2014, Stephane Debieux, USB Microcontroller firmware 
                Reply  Tue Oct 14 16:29:12 2014, Stefan Ritt, USB Microcontroller firmware 
                   Reply  Tue Oct 14 16:34:45 2014, Stephane Debieux, USB Microcontroller firmware 
                      Reply  Tue Oct 14 16:38:14 2014, Stefan Ritt, USB Microcontroller firmware 
                         Reply  Tue Oct 14 16:51:37 2014, Stephane Debieux, USB Microcontroller firmware 
Entry  Mon Sep 15 16:24:41 2014, Hannes Wachter, Timing Calibration Fail 
    Reply  Mon Sep 22 15:04:37 2014, Stefan Ritt, Timing Calibration Fail 
Entry  Fri Sep 12 14:57:22 2014, Dmitry Hits, compilation error for v5.0.2 
    Reply  Fri Sep 12 16:08:49 2014, Stefan Ritt, compilation error for v5.0.2 
       Reply  Fri Sep 12 16:38:24 2014, Dmitry Hits, compilation error for v5.0.2 
          Reply  Mon Sep 22 14:52:21 2014, Stefan Ritt, compilation error for v5.0.2 
Entry  Fri Sep 12 11:52:21 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer 
    Reply  Fri Sep 12 13:00:04 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer 
       Reply  Fri Sep 12 13:37:42 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer 
          Reply  Fri Sep 12 13:41:43 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer 
Entry  Thu Aug 21 11:03:36 2014, Martin Petriska, 10GSps on DRS4 Evm with delay cables 
    Reply  Tue Aug 26 12:32:21 2014, Stefan Ritt, 10GSps on DRS4 Evm with delay cables 
ELOG V3.1.5-3fb85fa6