Tue Jan 29 14:43:44 2019, Abaz Kryemadhi, ROOT Macro for data acquired with the newest software
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Hello,
Is there a root macro for decoding binary data acquired with the newest software for single board or multi-boards daisy chained?
Cheers, |
Wed Jan 30 17:08:58 2019, Stefan Ritt, ROOT Macro for data acquired with the newest software
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This one elog:361 should still work.
Stefan
Abaz |
Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study
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We have been using DRS4 IC in our design for quite some time and it is giving good performance.
Till now we were using Domino wave frequency as 1 GSPS by use of reference clock to DRS4 and internal PLL of DRS4. Recently we tried to use 4GSPS
by modifying the reference clock. |
Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study
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The Domino wave is most stable at 5 GSPS, slowly degrades down to 3-2 GSPS, and at 1GSPS gets some significant jitter. This is for internal reasons in
the chip and cannot be compensated by the loop filter. It is therefore important to run it as fast as possible if you want to achieve best timing resolution.
As a rule of thumb, the jitter at 5 GSPS is about 20-25 ps, and at 1 GSPS it is maybe 150 ps. If you require good timing resolution, you can use the 9th |
Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue
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Hi,
We are using the DRS4 Evaluation Board as a digitizer in our laboratory.
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Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue
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That's not a bug, but a feature of the DRS4 chip. The time bins have different values by the properties of the chip. They are generated by a chain of inverters,
which all have different propagation times. This delay is measured by the time calibration and then applied. If you want equidistant bins,
you have to interpolate your data points (linearly or by splines) and resample the signal. You can find more details in the DRS4 data sheet.
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Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue
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Thanks a lot for the quick response.
We will do as you suggest.
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Mon Nov 5 17:17:08 2018, Sean Quinn, Pi attenuator on eval board inputs?
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Dear DRS4 team,
I am curious about this part of the circuit: |
Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs?
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The attenuator compensates for the gain of the buffer which is slightly above one. In addition, it serves as a "placeholder" in case one wants
larger input signals. One can easily convert the attenuator to -6db, -12db, etc. by chaning the resistors.
Stefan |
Sun Sep 23 02:22:46 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms
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Hello Stefan,
I am using the DRS4 board connected to a Raspberry PI and through the drsosc application. I am interested on using the "Trigger OUT"
signal to do some extra data processing with NIM modules. According to the manual, for each hardware trigger a TTL pulse of 150 ns width should be send |
Wed Sep 26 14:44:14 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms
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The "Trigger OUT" has changed recently. It goes high on a new trigger, but then STAYS high until the board has been read out by the PC and
re-started. This allows better synchronization with some external trigger, which can be re-armed with the falling edge of the trigger out signal. The signal
can be quite long, since readout of an event via USB typically takes 2 ms, but can be more if the PC is busy. If you need back your 150 ns pulse, |
Wed Sep 26 18:28:20 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms
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Thank you very much for the answer, I really appreciate your help.
Thanks!
Gerard |
Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms
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In meantime I even updated the manual.
Stefan
Gerard |
Thu May 17 13:29:34 2018, Stefan Ritt, "Symmetric spikes" fixed
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Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.
The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel,
symmetric around sampling cell #512. See first attachment. |
Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed
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Hi,
Is it possible to fix it by FPGA changes? I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly
put this three commands. Could you please attach app.vhd file for eval board with example how to fix ? |
Tue Sep 4 13:04:30 2018, Stefan Ritt, "Symmetric spikes" fixed
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Yes it's possible, but I have to find time for that. The software of the evaluation board takes care of the spikes ("remove spikes"), so
I thought it's not so urgent to fix that in the FPGA (which takes me some time).
Stefan |
Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed
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Ok, so I made it ... and Yes it works :),
https://youtu.be/0noy4CoFoh8
here is changed part in drs4_eval4_app.vhd |
Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed
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Dear DRS4 team,
On page 3 of the data sheet, Table 1. for readout speed a typical value of 10 MHz is specified, but in the comment column it notes optimal performance
achieved at 33 MHz. |
Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed
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The analog output of the DRS4 chip needs some time to settle. In principle it need an infinite amout of time (exponential curve) to settle to 100% of
the final value. So if we sample after a finite time, there is some error we do. Some of the error will be taken care of the voltage calibration, but there
remains some residual error depending on the value of the previous sampling cell. So all sampling speeds 10 MHz, 16 MHz, 33 MHz are kind of rule of thumbs. |
Mon Aug 13 19:44:59 2018, Martin Petriska, Latch delay support
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Hi,
https://forge.physik.rwth-aachen.de/projects/drs4-rwth
Not sure about their licensing, but is it possible to add latch delay support to official firmware ? |
Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support
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I put that on the wish list, but I won't have time for that in the next months.
Stefan
Martin |
Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing
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Using a test pulse split into two channels of the DRS4 Evaluation Board v5, I looked at the time resolution using a leading edge threshold.
The voltage and timing calibration was performed. One method (1) is to linearly interpolate between two points of the raw waveform that
is above and below the threshold (this is exactly the algorithm given in read_binary.c in the drs4 source distribution); and another (2) is to |
Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing
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Just a follow-up update.
It turns out that I was using a cubic spline interpolation with smoothing. If I required the cubic spline to go through the sampled points, then
I obtained similar time resolution as the simple linear interpolation. |
Thu Jun 28 19:55:45 2018, Woon-Seng Choong, Negative Bin Width
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I am using a DRS4 Evaluation Board v5 and running the drsosc.exe version 5.06 on a Window 7 machine. I have performed the voltage and timing calibration.
With test pulses on channel 1 and 2, I collected binary data file with all 4 channels active sampling at 5GSPS.
Attached is a distribution of the bin_width vs. cell # for all the 4 channels. Note that there are few cells with bin_width < 10 ps. |
Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width
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Yes that's normal. A negative cell bin width means that the next cell N+1 samples the input signal before cell N. This can happen due to the signal
routing on the DRS4 chip.
Stefan |
Tue Jun 19 06:42:23 2018, Phan Van Chuan, The data acquisition speed
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Dear Stefan,
We are using an DRS4 board V5.1 for building a metering system for the scintillator detector by a Labview program. The program was built based
on the functions in DRS.cpp and it reads data from channel 0 very well (Fig 1). Now, I am having a problem with the data acquisition from DRS4 board. The |
Tue Jun 19 10:05:50 2018, Stefan Ritt, The data acquisition speed
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How do you tigger the board? In your code below you start the board (StartDomino()) and then wait for a trigger. Setting the trigger level to zero (via
SetTriggerLevel(0)) is certainly wrong. Please have a look at drs_exam.cpp in the distribution and use the same functions used there. If you want to trigger
the board, you need some external pulser with high enough rate (more than 500 Hz or course). You can also "software" trigger the board with a |
Tue Jun 19 12:54:51 2018, Phan Van Chuan, The data acquisition speed
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Thank Stefan Ritt, I added the SoftTrigger() just after StartDomino(), so now, The data acquisition speed the same speed as in the DRS oscilloscope.
I have misunderstood the "auto" trigger on an oscilloscope as setting SetTriggerLevel (0).
Thank so much! |
Wed Jun 13 13:23:17 2018, Julian Kemp, Maximum analog input voltage
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Dear all,
I have been wondering what the maximum analog input voltage for the DRS4 V5 evaluation board is. It came with a sticker indicating that it is
"2.5V pk Max". On the other hand, when checking the manual (https://www.psi.ch/drs/DocumentationEN/manual_rev50.pdf), it says maximum allowed |
Wed Jun 13 13:42:47 2018, Stefan Ritt, Maximum analog input voltage
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In principle the numbers in the manual are correct. But they relate to pulses of a certain length, because the input protection only works for DC voltage
and for pulses which are not too long. Since we could not write this all on the label of the board, we decided to put there 100% safe value as a "warning"
to people, meaning that if pulses are above 2.5V, they should look into the manual and read the details. |
Wed Jun 13 16:34:28 2018, Julian Kemp, Maximum analog input voltage
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Thank you! That solves my problem.
Stefan
Ritt wrote:
In principle the numbers in the manual are correct. But they relate |
Thu Jun 7 16:27:21 2018, Phan Van Chuan,
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Dear Stefan,
I am using an DRS4 board to test the signal from an scintillator detector; It has connected well to the computer on DRS Oscilloscope (Figure
1). Now, I am having a problem of developing from the code of the drs_exam program, because the DRS4 board has not connected to the computer when translation |
Fri Jun 8 08:11:05 2018, Stefan Ritt,
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Several people reported this problem, but we cannot reproduce it at our lab. Both the oscilloscope and the command line interface use exactly the same
code to connect to the board. Have you tried the solution reported here: elog:657 ?
Best, |
Tue Feb 27 13:17:00 2018, Steven Block, WIndows Connection problem with drs507 SOLVED
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Hello All,
I too have been struggling with trying to get the drs4 (507) to work on my windows machine and I found it to be a problem with the libusb library.
My solution is as follows and has worked on multiple PC's. I ran this solution after I first plugged in the drs4 and installed 507. |
Tue Feb 27 13:29:47 2018, Stefan Ritt, WIndows Connection problem with drs507 SOLVED
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Dear Steven, many thanks for this information, this is very useful. I know of people having problems on Windows 10, maybe this will also help them.
Stefan
Steven |
Wed May 9 14:07:10 2018, Alec Shackleford, WIndows Connection problem with drs507 SOLVED
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Thank you for this fantastic solution. I had almost reinstalled windows 7 to see if that would solve the issue!
All the best, |
Mon May 14 09:21:29 2018, Alessio Berti, WIndows Connection problem with drs507 SOLVED
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Hi,
I have a machine with Windows 10 and the solution provided by Steven works fine. To give more details, the driver installed in my case is WinUSB
(i.e. libusb, v6.1.7600.16385). |
Tue May 8 23:58:35 2018, Sean Quinn, Manual Rev5.1 Figure 1, optional components
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Dear All,
I'm troubleshooting a board which uses the DRS4 and adopts an analog front end very similar to the evaluation board. As a result, we rely |
Wed May 9 09:03:52 2018, Stefan Ritt, Manual Rev5.1 Figure 1, optional components
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I updated the picture in the manual with a current picture of a Rev5.1 board, and also added a picture of the bottom side. If you need a picture without
the blue labels, have a look at https://www.psi.ch/drs/old-evaluation-boards at the bottom.
Here is the explanation of the optional components: |
Wed May 2 10:44:17 2018, Alessio Berti, Peak at 0 mV in traces
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Hi,
we modified drs_exam.cpp to read all 4 channels from the DRS4 and apply directly the spike removal (taken from Osci.cpp) during the acquisition
phase. For test purposes, we don't save the data showing spikes and we focus on the data not having spikes (even if at the end we end up having triple |
Wed May 2 12:12:42 2018, Stefan Ritt, Peak at 0 mV in traces
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I note that your peak at zero is exactly twice as high as the bins left and right, so this looks to me like a binning problem in your histogramming.
Maybe your bin #0 goes from -1mV to +1mV, which all other bins are just 1mW wide. Can you check that?
Stefan |
Wed May 2 12:23:16 2018, Alessio Berti, Peak at 0 mV in traces
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Hi,
thank you for the quick reply. All the bins in the previous histograms have the same width. We also tried to plot the noise histogram for channel
2 with more bins (i.e. 1000, so that we can see almost discrete values), and the peak is still there. |
Fri May 4 11:35:20 2018, Stefan Ritt, Peak at 0 mV in traces
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I tried the following:
- trigger on a 10 MHz sine wave on CH0, CH1 was open
- run drs_exam.cpp program and write data.txt with a few events |
Tue May 8 12:15:54 2018, Alessio Berti, Peak at 0 mV in traces
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Hi Stefan,
following your example, we tried to perform the same measurement, using drs_exam and taking 1000 events. The results we obtained are in the plots
attached (both in log and linear scale). We tried two different binnings: |
Tue May 8 14:43:03 2018, Stefan Ritt, Peak at 0 mV in traces
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The DRS chip is read out with a 12 bit ADC, thus the phyical resolution is roughly 1V/4096 = 0.24 mV. I say roughly since the DRS has an analog gain
of 0.98, which is corrected for. Now you have integer values which are converted into floating point numbers my multiplying them with ~0.24mV. If you then
do histogramming with different bin sizes such as 0.1 mV and 0.35 mV , you get aliasing effects. The code truncates the result to 0.1 mV, which can give |
Wed Mar 14 09:13:39 2018, chen wenjun, confusion about the description in drs.cpp
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Hi,Stefan:
recently,whtn I study the drs.cpp code ,I found that the buffer[1] is char but the addr and the base_addr are all unsigned int,isn't
there any problem that the addr may be cut off to 8 bits? Also ,I found that the data fpga recieved from the usb is 16 bits,so how can fpga get the true |
Fri Mar 16 14:00:06 2018, Stefan Ritt, confusion about the description in drs.cpp
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The FPGA is very small, so it only has an address space of 256 bytes. Look at the definition in DRS.cpp
#define USB_CTRL_OFFSET
0x00 /* all registers 32 bit */ |
Sun May 6 08:13:37 2018, chen wenjun, confusion about the description in drs.cpp
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Hi Stefan:
I'm still confused that althought the 8 bits buffer is enough,the FPGA receive the command through the uc_data_i register which is
16 bits wides.As we can see in the firmware, the locbus_addr is 32 bits wides. Does it means the locbus_addr[31:8] are always '0' because the address |
Sun May 6 11:45:09 2018, Stefan Ritt, confusion about the description in drs.cpp
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The locbus_addr is indeed 32 bits wide, since the firmware was originally derived from some firmware running in a VME crate, and the VME bus has 32 bits
or addressing. So you will still find some "historic" remnants from that era. In the USB firmware, lcobus_addr[32:8] is always zero. Sorry for
the confusuion. |
Fri Apr 13 18:14:07 2018, Alessio Berti, Voltage and Timing Calibration in drs_exam.cpp
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Hi,
we were trying to implement an automatic way to calibrate our DRS4 both in voltage and in time (we have the V5 Evaluation Board). We started
from drs_exam.cpp and tried with the following lines: |
Fri May 4 11:56:08 2018, Stefan Ritt, Voltage and Timing Calibration in drs_exam.cpp
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Have you set the sampling frequency
b->SetFrequency(5, true);
before the calibration? |
Tue May 1 02:00:40 2018, Hyunseong Kim, DRS4 using drs_exam.cpp to save as binary files
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Hi,
I would like to save the waveform in a .dat binary file using drs_exam.cpp.
I know the distributed software allows us to save as binary files with the save button, but I currently need to save multiple runs using |
Wed May 2 09:24:53 2018, Stefan Ritt, DRS4 using drs_exam.cpp to save as binary files
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You have to write the C/C++ code yourself to write data in binary or any other format. All information is present after the waveform readout in drs_exam.cpp,
so it's just a matter of proper write() functions. Please consult any C/C++ handbook on how to write to files.
Hyunseong |
Mon Apr 16 21:21:29 2018, Sobimpe Eniola, DRS4 read_binary.cpp
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Hello everyone,
The new read_binary.cpp code
I will be very glad if anyone can help with the old version of read_binary.cpp code. The latest version I saw online was updated on June |
Tue Apr 17 13:28:23 2018, Stefan Ritt, DRS4 read_binary.cpp
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On the software download page at https://www.psi.ch/drs/software-download you find a link to all versions of the DRS software, which is located
at: https://www.dropbox.com/sh/clqo7ekr0ysbrip/AACoWJzrQAbf3WiBJHG89bGGa?dl=0
Earch .tar.gz file has a date, which should help you find the correct version. |