 Wed Oct 26 21:15:35 2016, Alexey Lubinets, Problems with DRS command line
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Hello, everybody
I have installed the software for the DRS4 Evaluation Board.
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 Thu Oct 27 08:29:26 2016, Stefan Ritt, Problems with DRS command line
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[quote="Alexey Lubinets"]Hello, everybody
I have installed the software for the DRS4 Evaluation Board.
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Fri Oct 28 15:02:18 2016, Simon Mendisch, Problems with DRS command line
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[quote="Stefan Ritt"]
You are the first one describing this problem (out of ~200 people), so I guess the problem must be on your side. Have you made sure to start the DRS oscilloscope
and the Command Line Interface not at the same time? Only one program can access the board at a given time. Have you tried disconnecting and re-connecting |
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Fri Oct 28 15:51:59 2016, Stefan Ritt, Problems with DRS command line
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No, I absolutely have no idea. Both DRSOsc and drscl use exaclty the same code to access USB.
Stefan
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Tue Oct 11 22:11:26 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Thank you very much! I will check it tomorrow!
-d
Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker |
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Sun Oct 9 10:43:35 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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(Board Type:9, DRS4)
Hello,
I´m trying to reach the timig resolution of about 2.5ps as written in the manual. |
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Sun Oct 9 11:39:18 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Can you post a screenshot of your measurement?
Stefan
Danny |
Mon Oct 10 11:30:37 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
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Hello Stefan,
Chn2 & Chn3 were used for delay-determination as you can see on the second picture.
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Mon Oct 10 12:03:27 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Ok, I got it. The timing resolution is affected by the signal-to-noise ratio over the rise-time of your signal. You find the full formula herer:
https://arxiv.org/abs/1405.4975
Your sine wave input signal has a slow rise time, and therefore limits the time resolution. I reproduced your measurement with a 20 MHz sine |
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Tue Oct 11 09:04:33 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Hello Stefan,
thanks for the paper. That makes sense. I thought about sth. like that but wasn`t sure. Couldn´t check higher frequencies (limit of my
function generator). |
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Tue Oct 11 09:20:04 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Concerning the offset, it looks to me like you moved the offset slider slider of channel 1 to a non-zero position. You see that from the marker at the
very left side of the screen, where the yellow marker is at a different position as the others. Hint: a right-click on that slider sets it to zero. The
little streak could be some kind of external noise. |
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Thu Oct 6 15:23:18 2016, Will Flanagan,
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Hi Stefan,
That is exactly what I'm looking for. Thanks again!
Will |
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Wed Oct 5 22:43:29 2016, Will Flanagan, Timestamp for each DRS4 waveform
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Hi DRS4 Experts,
I have been analyzing DRS4 binary data with scripts based on Stefan's (very helpful!) macro:
https://midas.psi.ch/elogs/DRS4+Forum/361 |
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Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform
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In the mentioned read_binary.cpp file you have the line where you read the event header
i = fread(&eh, sizeof(eh), 1, f);
The C structure eh now contains the full timestamp, and you can access it with |
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Thu Sep 29 17:26:13 2016, Jacob Hwang, Output Timing Drifting
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Hello,
I have designed four DRS4 chips (36 channels) on my board running at 1GHz (REFCLK=488.28KHz) and ROI mode. All 4 chips' REFCLK, DWRITE, RSRLOAD,
and SRCLK are buffer driven by the same source. SRCLK is set to 40MHz to reduce the readout time. |
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Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting
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Hi Jacob,
you are missing the timing calibration. Each sampling cell has not the same width. Running at 5 GSPS, cell widths scatter from 150 ps to 250
ps. If you integrate these widhts, you get a time scale which can be off by a few ns between chips, something you see in your plot. Here is a paper which |
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Mon Aug 29 09:36:34 2016, benjamin legeyt, increment write config register on the fly?
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Hello,
I have a question about using the write config register to enable/disable sampling on the fly. I am looking to instrument an experiment
at EPFL where multiple short events need to be captured during a 20us period followed by an 80us quiet period during which we could read out the chip. |
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Mon Aug 29 10:57:33 2016, Stefan Ritt, increment write config register on the fly?
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The issue with "stopping at cell 767" would also affect this mode of operation. Furthermore, the DRS4 chip has only 10 bit register which
records in which cell the event has occured, and where the readout must be started. If you record 8 separate events, you don't know where to start
the readout. |
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Mon Aug 29 12:18:49 2016, benjamin legeyt, increment write config register on the fly?
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If I may trouble you for a little more information, the critical point then is that there should not be any zeroes in the write config register
while the sampling is active? In case it was unclear I would only be reading out once sampling was stopped (dwrite = 0).
As for the readout, I know that I would have to read out all 1024 samples each time, and keep track of where each channel stopped in the FPGA. |
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Mon Aug 29 12:51:48 2016, Stefan Ritt, increment write config register on the fly?
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The problem is when you change the write config register from 11111111 to 01111111, or from 00001111 to 00000111, then the last 256 sampels of the previous
channel (in the first case #0, in the scond #4) would be overwritten as soon as dwrite =1 again. So you loose 1/4 ef each channel.
Concerning the readout, indeed you can keep track in the FPGA, but only with a certainty of a few cells. This gives some timing inacccuracy of |
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Wed Jun 29 09:10:01 2016, Stefan Ritt, Negative input signals
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Hello everybody,
I get often asked if the DRS4 evaluation board can accomodate negative input pulses going to -1V. This is unfortunately not possible, since the
board is mainly for evaluation of the DRS4 chip and should not be seen as a complete oscilloscope with flexible input stage. So the maximum it can do is |
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Sun Jun 12 08:45:52 2016, Michael, problems of DRS4
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Hi
I want to use DRS4 to digitize 16 channels of signals. The width of signal is about 20 ns, with frequency of 50Hz. The time differences
between these 16 signals are not constant, arranging from 3us to 0. I am confused about this in some aspects. |
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Wed Jun 15 14:49:00 2016, Stefan Ritt, problems of DRS4
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1. Simultaneous writing and reading is not possible with the DRS4 chip. The manual says differently on p. 14, but due to a bug in the chip waveforms
get clipped at the end if one does that. We hopt to fix this problem in a future version of the chip.
2. You can cascade 2,4 or 8 channels. If you cascade 8 channels and run at 1 GSPS, you digitize a window of 8 us. If you have 16 signals, you |
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Sun Jun 12 08:49:54 2016, Michael, problems of DRS4
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Hi
I want to use DRS4 to digitize 16 channels of signals. The width of signal is about 20 ns, with frequency of 50Hz. The time differences
between these 16 signals are not constant, arranging from 3us to 0. I am confused about this in some aspects. |
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Wed Jun 1 22:29:01 2016, Dominik Neise, problems when stop cell >= 767 ??
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Hello Stefan,
some colleages told me a story, I was neither able to confirm nor find anything in the datsheet about. According to them:
For some internal reason of the DRS4, if the “stop capacitor” of the DRS4 is >= 767, the true stop channel is one |
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Wed Jun 1 23:16:01 2016, Stefan Ritt, problems when stop cell >= 767 ??
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I cannot confirm the story with the "stop capacitor > 767". It can be seen from your plots that the distribution of stop cells are even,
no holes or bins with double height.
There is an issue with cell 767, but this is when one tries to do simultaneous reading/writing to the chip. This does not really work as writen |
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Wed May 11 04:01:14 2016, Maksat, DRS4 Macro to save events
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Dear Stefan,
I am trying to setup DRS inside radiation enclosure and would like to write a simple script that will automatically save certain number of events.
Could you please point to me an example that can I use for Mac OS? I saw there is drs_exam.cpp in the directory but was not able to get work |
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Thu May 12 12:38:17 2016, Stefan Ritt, DRS4 Macro to save events
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Dear Maksat,
If your car does not run, and you call the car dealer and tell him "my car does not run", what will the car dealer ask you? Eh... ?
Right ! He will ask "what are the symptoms, what did you try, what did and what did not work". Here it's the same. "was not able to |
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Thu May 12 05:18:47 2016, Yu, Problem For Software Download
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Hi
I can't download the software for windows on this website 'www.psi.ch/drs/software-download', there is some mistake when i
click on download. |
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Thu May 12 08:16:41 2016, Stefan Ritt, Problem For Software Download
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Can you tell me (screendump) what is the problem on the web site https://www.psi.ch/drs/software-download ?
It should redirect you to
https://www.dropbox.com/sh/qul1cgtm4x7zx13/AADKQ-qGQGdAHPu6OR3vTNY0a?dl=0 |
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Wed May 11 15:48:57 2016, SANDJONG Saturnin Orly, Probléme de Calibration de la DRS4
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Bonjour, Je suis en stage dans un laboratoire ou on utilise pour echantillonnage des données, une cartes DRS4 5GSPS avec 1024 cell, mon probléme
réside dans la partie Calibration en tension selon l'article "Novel Calibration Method for Switched Capacitor Arrays Enables Time
Measurements with Sub-Picosecond Resolution". |
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Mon Feb 29 13:33:06 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each
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Dear Stefan,
I daisy-chained two boards (master sn#: 2514 - slave sn#: 2513) each with 2048 samples. However, when I use drsosc and put check mark in "configure
multi-board daisy-chain" I see only 1024 samples. Namely, the first 1024 samples, the last part is missing. When I remove this check mark, I |
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Mon Feb 29 14:09:21 2016, Stefan Ritt, two DRS4 boards configuration with 2048 samples each
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The multi-board mode has never been tested with 2048 samples, so is very likely not to work. I don't know yet how much work this will be to
fix, but I'm on a business trip the next three weeks and probably will only have time to look at it when I return.
Stefan |
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Mon May 2 14:31:28 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each
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Hi Stefan
Any chance you have time to fix the software for multiboard configuration with 2048 samples each. I tried 5.0.5, but drsosc still shows
only half of the waveform. |
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Thu Apr 28 15:47:53 2016, Stefan Ritt, New software version and binary format
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A new software version 5.0.5 has been released today. This fixes a few bugs in multi-board configurations, and adds saving of the scaler values into
XML and binary files. Please note that the binary file format has been changed for that. The new format is described in an updated manual (page
25), and reflected in a new read_binary.cpp program contained in the distribution. |
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Wed Apr 27 20:04:12 2016, Abaz Kryemadhi, Best settings for time measurements
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I am studing some pulses that are about 200-300 ns wide and a rise time of few ns, which settings would be best for coincidence time
measurements?
In some preliminary work I found for 700 MegaS the time measurement is better without time calibration (in -0.05 to 1V) rather than with time |
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Thu Apr 28 15:46:34 2016, Stefan Ritt, Best settings for time measurements
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The DRS4 chip has been designed to work best at high sampling speeds. At 700 MSPS, the chip is at it's limit and timing is very poorr (ns?). In order
to get good timing, run it at least at 2 GSPS.
Stefan |
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Wed Apr 27 08:14:14 2016, Toshihiro Nonaka, serial number problem
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Dear all,
I'm using 3 DRS boards simultaneously and their serial numbers are 2169, 2170, 2172 respectively.
Recently however, I obtain serial number "0" by DRSBoard::GetBoardSerialNumber() for #2172 board. |
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Wed Apr 27 09:04:01 2016, Stefan Ritt, serial number problem
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If dis- and reconnecting the board does not help, there is the (small) chance that the serial number got erased in the board. You can re-set it with
the "drscl" command line tool:
$ drscl |
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Wed Apr 27 09:51:37 2016, Toshihiro Nonaka, serial number problem
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The serial number has been fixed by using drscl. Thank you！
Stefan
Ritt wrote:
If dis- and reconnecting the board does not help, there is the (small) |
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Fri Apr 15 12:58:46 2016, Konstantin Gusev, DRS4 purchase information
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Hi,
I can't contact with Anita Van Loon about DSR4 chip's price and delivery.
Did you still sell it? Can you provide me this information? |
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Tue Apr 26 13:42:42 2016, Stefan Ritt, DRS4 purchase information
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Just be patient. Anita is not at work this week.
Konstantin
Gusev wrote:
Hi, |
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Thu Apr 21 22:16:43 2016, Kyle Weinfurther, Negative fCellDT values from GetTimeCalibration()
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Hello Stefan,
I am using four DRS4 v5 eval boards to digitize 16 channels of data. I have recently changed from saving the timing information of the waveform
using GetTime() to GetTimeCalibration(). When changing over, I noticed that some values for fCellDT for cell 498 are negative. Over the 16 channels used, |
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Sat Apr 23 12:33:17 2016, Daniel Stricker-Shaver, Negative fCellDT values from GetTimeCalibration()
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Hi Kyle,
If I remember right the negative sampling width happens only for 498 and at high sampling speeds. It is described in a paper from Stefan:
http://arxiv.org/pdf/1405.4975.pdf |
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Tue Apr 26 09:54:16 2016, Stefan Ritt, Negative fCellDT values from GetTimeCalibration()
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I just realized that the negative bin widht is not explicitly mentioned in the quoted paper. So let me explain it here:
The negative value of cell 498 is correct and "real" in the sense that the signal is first captured in cell 498 and later
in cell 497. This is due to the exact layout of the cells on the chip and the input signal. Cell 498 is simply much closer to the input, so sees the |