DRS4 Forum
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Entry  Wed Oct 23 17:56:26 2019, John Jendzurski, Computing corrected time from binary data...what is t_0,0? Screenshot.png
    Reply  Fri Oct 25 16:39:07 2019, Stefan Ritt, Computing corrected time from binary data...what is t_0,0? 
Entry  Mon Oct 14 09:32:33 2019, Danyang, how to acquire the stop position with channel cascading Capture.PNG
    Reply  Mon Oct 14 10:14:46 2019, Stefan Ritt, how to acquire the stop position with channel cascading 
       Reply  Mon Oct 14 11:45:06 2019, Danyang, how to acquire the stop position with channel cascading Capture.PNG
          Reply  Mon Oct 14 12:56:13 2019, Stefan Ritt, how to acquire the stop position with channel cascading 
             Reply  Mon Oct 14 13:44:26 2019, Danyang, how to acquire the stop position with channel cascading 
                Reply  Mon Oct 14 15:27:09 2019, Stefan Ritt, how to acquire the stop position with channel cascading 
                   Reply  Tue Oct 15 08:14:17 2019, Danyang, how to acquire the stop position with channel cascading 
Entry  Fri Sep 13 15:27:41 2019, Arseny Rybnikov, Scaler / How to modify the firmware to change the scaler integration time 
Entry  Tue Aug 27 08:33:22 2019, chinmay basu, DRS4 
    Reply  Tue Aug 27 09:14:03 2019, Stefan Ritt, DRS4 
Entry  Mon Aug 19 23:01:22 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register? 
    Reply  Tue Aug 20 10:44:45 2019, Stefan Ritt, should one deassert DENABLE while writing the write-shift register? 
       Reply  Tue Aug 20 16:05:21 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register? 
Entry  Thu Jul 18 01:03:44 2019, Ismael Garcia, Trace Impedance DRS4_Analog_IN.PNG
    Reply  Thu Jul 18 11:37:56 2019, Stefan Ritt, Trace Impedance 
       Reply  Fri Jul 19 01:37:09 2019, Ismael Garcia, Trace Impedance 
          Reply  Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance 
Entry  Sat Jul 13 01:00:15 2019, Brendan Posehn, Evaluation Board Test Functionality 
    Reply  Mon Jul 15 17:26:50 2019, Stefan Ritt, Evaluation Board Test Functionality 
       Reply  Mon Jul 15 19:34:25 2019, Brendan Posehn, Evaluation Board Test Functionality 
Entry  Tue Jun 25 23:04:29 2019, Si Xie, drs_exam is always reading out a sin wave 
    Reply  Wed Jun 26 13:08:42 2019, Stefan Ritt, drs_exam is always reading out a sin wave 
       Reply  Wed Jun 26 15:10:09 2019, Si Xie, drs_exam is always reading out a sin wave 
          Reply  Mon Jul 8 14:29:12 2019, Stefan Ritt, drs_exam is always reading out a sin wave 
Entry  Wed Mar 7 22:49:38 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp drs_exam.cpp
    Reply  Thu Mar 8 22:54:20 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp 
       Reply  Fri May 4 12:11:57 2018, Stefan Ritt, Running drs_example.cpp 
       Reply  Wed Jun 26 15:17:51 2019, Si Xie, Running drs_example.cpp 
    Reply  Mon Mar 19 15:12:02 2018, Stefan Ritt, Running drs_example.cpp 
Entry  Thu Jun 20 01:36:48 2019, Andrew Peck, Evaluation firmware wait_vdd state 
    Reply  Fri Jun 21 12:54:47 2019, Stefan Ritt, Evaluation firmware wait_vdd state 
       Reply  Mon Jun 24 23:07:35 2019, Andrew Peck, Evaluation firmware wait_vdd state 
Entry  Fri Apr 12 09:39:30 2019, Lev Pavlov, multi-board 
    Reply  Fri Apr 12 09:55:50 2019, Stefan Ritt, multi-board 
       Reply  Fri Apr 12 09:59:15 2019, Lev Pavlov, multi-board 
          Reply  Fri Apr 12 12:50:18 2019, Stefan Ritt, multi-board 
Entry  Thu Mar 14 03:43:49 2019, Deepak Samuel, How to buy DRS evaluation kit 
Entry  Fri Mar 8 19:35:11 2019, Abaz Kryemadhi, ROOT Macro for newest software read_binary.C
Entry  Wed Mar 6 10:09:01 2019, Willy Chang, drscl "no board found" in some Win7 or Win8.X PCs 
Entry  Wed Feb 20 08:03:04 2019, Lev Pavlov, meg? 
    Reply  Wed Feb 20 08:08:42 2019, Stefan Ritt, meg? 
       Reply  Wed Feb 20 12:13:44 2019, Lev Pavlov, meg? 
          Reply  Wed Feb 20 12:56:56 2019, Stefan Ritt, meg? 
             Reply  Thu Feb 21 09:51:24 2019, Lev Pavlov, no board found 
                Reply  Thu Feb 21 09:57:53 2019, Stefan Ritt, no board found 
                   Reply  Mon Feb 25 08:40:44 2019, Lev Pavlov, no board found 
                      Reply  Mon Feb 25 08:48:27 2019, Stefan Ritt, no board found 
Entry  Mon Feb 4 16:42:08 2019, Hans Steiger, Different Distances between the sampling points 
    Reply  Mon Feb 4 16:46:04 2019, Stefan Ritt, Different Distances between the sampling points 
       Reply  Mon Feb 4 17:36:49 2019, Hans Steiger, Different Distances between the sampling points 
          Reply  Mon Feb 4 18:18:22 2019, Stefan Ritt, Different Distances between the sampling points 
Entry  Sat Feb 2 00:13:12 2019, Hans Steiger, Saving Rate (only 15Acq/s) 
    Reply  Sat Feb 2 10:10:22 2019, Stefan Ritt, Saving Rate (only 15Acq/s) 
Entry  Tue Jan 29 14:43:44 2019, Abaz Kryemadhi, ROOT Macro for data acquired with the newest software 
    Reply  Wed Jan 30 17:08:58 2019, Stefan Ritt, ROOT Macro for data acquired with the newest software 
Entry  Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study 
    Reply  Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study 
Entry  Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue 
    Reply  Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue 
       Reply  Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue 
Entry  Mon Nov 5 17:17:08 2018, Sean Quinn, Pi attenuator on eval board inputs? pi_att.PNG
    Reply  Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs? 
Entry  Sun Sep 23 02:22:46 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms 
    Reply  Wed Sep 26 14:44:14 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms 
       Reply  Wed Sep 26 18:28:20 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms 
          Reply  Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms 
Entry  Thu May 17 13:29:34 2018, Stefan Ritt, "Symmetric spikes" fixed with.pngScreen_Shot_2018-05-17_at_13.30.23_.pngwithout.png
    Reply  Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed 
       Reply  Tue Sep 4 13:04:30 2018, Stefan Ritt, "Symmetric spikes" fixed 
          Reply  Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed 
Entry  Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed eval51_adc_50ns.png
    Reply  Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed 
Entry  Mon Aug 13 19:44:59 2018, Martin Petriska, Latch delay support 
    Reply  Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support 
Entry  Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing 
    Reply  Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing 
Entry  Thu Jun 28 19:55:45 2018, Woon-Seng Choong, Negative Bin Width bin_width_5gsps.jpgtest5gsps.dat
    Reply  Fri Jun 29 07:51:33 2018, Stefan Ritt, Negative Bin Width 
Entry  Tue Jun 19 06:42:23 2018, Phan Van Chuan, The data acquisition speed wavech0.png
    Reply  Tue Jun 19 10:05:50 2018, Stefan Ritt, The data acquisition speed 
    Reply  Tue Jun 19 12:54:51 2018, Phan Van Chuan, The data acquisition speed 
Entry  Wed Jun 13 13:23:17 2018, Julian Kemp, Maximum analog input voltage 
    Reply  Wed Jun 13 13:42:47 2018, Stefan Ritt, Maximum analog input voltage 
       Reply  Wed Jun 13 16:34:28 2018, Julian Kemp, Maximum analog input voltage 
Entry  Thu Jun 7 16:27:21 2018, Phan Van Chuan,  figure1.pngfigure2.png
    Reply  Fri Jun 8 08:11:05 2018, Stefan Ritt,  
Entry  Tue Feb 27 13:17:00 2018, Steven Block, WIndows Connection problem with drs507 SOLVED 
    Reply  Tue Feb 27 13:29:47 2018, Stefan Ritt, WIndows Connection problem with drs507 SOLVED 
       Reply  Wed May 9 14:07:10 2018, Alec Shackleford, WIndows Connection problem with drs507 SOLVED 
          Reply  Mon May 14 09:21:29 2018, Alessio Berti, WIndows Connection problem with drs507 SOLVED 
Entry  Tue May 8 23:58:35 2018, Sean Quinn, Manual Rev5.1 Figure 1, optional components 
    Reply  Wed May 9 09:03:52 2018, Stefan Ritt, Manual Rev5.1 Figure 1, optional components 
Entry  Wed May 2 10:44:17 2018, Alessio Berti, Peak at 0 mV in traces zero_peak_after_spike_removal_ch1.pngzero_peak_after_spike_removal_ch2.pngzero_peak_after_spike_removal_ch3.pngzero_peak_after_spike_removal_ch4.pngzero_peak_after_spike_removal_offset_correction_ch2.png
    Reply  Wed May 2 12:12:42 2018, Stefan Ritt, Peak at 0 mV in traces 
       Reply  Wed May 2 12:23:16 2018, Alessio Berti, Peak at 0 mV in traces zero_peak_after_spike_removal_ch2_1000_bins.png
          Reply  Fri May 4 11:35:20 2018, Stefan Ritt, Peak at 0 mV in traces Screen_Shot_2018-05-04_at_11.36.24_.png
             Reply  Tue May 8 12:15:54 2018, Alessio Berti, Peak at 0 mV in traces 20180508_drs4_drs_exam_1000_events_81_bins_linear.png20180508_drs4_drs_exam_1000_events_81_bins_log.png20180508_drs4_drs_exam_1000_events_23_bins_linear.png20180508_drs4_drs_exam_1000_events_23_bins_log.png
                Reply  Tue May 8 14:43:03 2018, Stefan Ritt, Peak at 0 mV in traces 
Entry  Wed Mar 14 09:13:39 2018, chen wenjun, confusion about the description in drs.cpp 20180314161201.jpg
    Reply  Fri Mar 16 14:00:06 2018, Stefan Ritt, confusion about the description in drs.cpp 
       Reply  Sun May 6 08:13:37 2018, chen wenjun, confusion about the description in drs.cpp 
          Reply  Sun May 6 11:45:09 2018, Stefan Ritt, confusion about the description in drs.cpp 
Entry  Fri Apr 13 18:14:07 2018, Alessio Berti, Voltage and Timing Calibration in drs_exam.cpp 
    Reply  Fri May 4 11:56:08 2018, Stefan Ritt, Voltage and Timing Calibration in drs_exam.cpp 
Entry  Tue May 1 02:00:40 2018, Hyunseong Kim, DRS4 using drs_exam.cpp to save as binary files 
    Reply  Wed May 2 09:24:53 2018, Stefan Ritt, DRS4 using drs_exam.cpp to save as binary files 
Entry  Mon Apr 16 21:21:29 2018, Sobimpe Eniola, DRS4 read_binary.cpp  
    Reply  Tue Apr 17 13:28:23 2018, Stefan Ritt, DRS4 read_binary.cpp  
Entry  Thu Mar 22 14:36:01 2018, Phan Van Chuan, Read the CalibrateWaveform 
    Reply  Fri Mar 23 09:39:55 2018, Stefan Ritt, Read the CalibrateWaveform 
Entry  Fri Mar 2 18:08:55 2018, Steven Block, ROI  
    Reply  Fri Mar 2 20:17:17 2018, Stefan Ritt, ROI  
       Reply  Fri Mar 2 21:05:48 2018, Steven Block, ROI  
          Reply  Mon Mar 19 16:22:42 2018, Stefan Ritt, ROI  
Entry  Wed Mar 14 00:38:15 2018, Will Flanagan, sub-ms precision timestamps? 
    Reply  Thu Mar 15 08:44:26 2018, Stefan Ritt, sub-ms precision timestamps? 
Entry  Tue Feb 27 16:34:26 2018, Steven Block, DRS4 Dead times 6x
    Reply  Tue Feb 27 17:04:12 2018, Stefan Ritt, DRS4 Dead times 
       Reply  Tue Feb 27 18:04:18 2018, Steven Block, DRS4 Dead times 
          Reply  Tue Feb 27 18:12:32 2018, Stefan Ritt, DRS4 Dead times 
Entry  Thu Jan 25 05:24:05 2018, chen wenjun, problem with the drscl(drs507) 
    Reply  Thu Jan 25 08:00:16 2018, Stefan Ritt, problem with the drscl(drs507) 
       Reply  Thu Jan 25 08:07:32 2018, chen wenjun, problem with the drscl(drs507) 
Entry  Tue Mar 28 21:53:12 2017, Jim Freeman, drscl doesn't find eval board but drsosc does (Windows 7) 
    Reply  Wed Apr 5 12:28:28 2017, Stefan Ritt, drscl doesn't find eval board but drsosc does (Windows 7) Screen_Shot_2017-04-05_at_12.27.46_.pngScreen_Shot_2017-04-05_at_11.45.07_.png
    Reply  Thu Jan 25 06:10:52 2018, chen wenjun, drscl doesn't find eval board but drsosc does (Windows 7) 
Entry  Wed Jan 17 09:51:16 2018, Tran Cong Thien, The input signals recorded are different with the signal showed in oscilloscope  
    Reply  Wed Jan 17 10:09:09 2018, Stefan Ritt, The input signals recorded are different with the signal showed in oscilloscope  
Entry  Tue Mar 26 01:17:59 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp 
    Reply  Thu Apr 4 11:32:21 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
       Reply  Fri Apr 5 02:21:33 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp 
          Reply  Fri Apr 5 08:54:37 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp Screen_Shot_2013-04-05_at_8.51.53_.png
             Reply  Wed Apr 10 22:41:21 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp 
                Reply  Thu Apr 11 08:39:12 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
                   Reply  Thu Apr 11 23:32:57 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp 
                      Reply  Fri Apr 12 08:25:05 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
                         Reply  Wed Dec 20 15:30:38 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp 
                            Reply  Wed Dec 20 16:21:42 2017, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
                               Reply  Wed Dec 20 16:30:45 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp 
                                  Reply  Wed Dec 20 22:14:35 2017, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
Entry  Tue Dec 12 00:25:50 2017, Diego Yankelevich, External trigger using Raspberry Pi 
    Reply  Tue Dec 12 13:58:06 2017, Stefan Ritt, External trigger using Raspberry Pi 
Entry  Thu Nov 16 02:55:44 2017, Diego Yankelevich, Averaging capabilities  
    Reply  Wed Nov 22 14:52:31 2017, Stefan Ritt, Averaging capabilities  
Entry  Wed Nov 22 08:31:03 2017, chen wenjun , using of the DRS Command Line Interface ΢ͼƬ_20171122153834.png
    Reply  Wed Nov 22 08:48:36 2017, Stefan Ritt, using of the DRS Command Line Interface 
       Reply  Wed Nov 22 08:58:33 2017, chen wenjun , using of the DRS Command Line Interface ΢ͼƬ_20171122160245.png
          Reply  Wed Nov 22 09:14:18 2017, Stefan Ritt, using of the DRS Command Line Interface 
             Reply  Wed Nov 22 09:19:11 2017, chen wenjun , using of the DRS Command Line Interface 
Entry  Fri Nov 3 12:11:14 2017, Hkan Wennlf, Triggering using AND 
    Reply  Fri Nov 3 13:28:04 2017, Stefan Ritt, Triggering using AND 
Entry  Tue Oct 17 14:58:58 2017, Vadym Denysenko, Time offset  
    Reply  Wed Oct 18 09:12:26 2017, Stefan Ritt, Time offset  
       Reply  Wed Oct 18 11:48:14 2017, Vadym Denysenko, Time offset  
Entry  Fri Oct 13 03:39:01 2017, Jonathan Wapman, Raspberry Pi Connection Failure 
    Reply  Mon Oct 16 15:35:22 2017, Stefan Ritt, Raspberry Pi Connection Failure 
Entry  Wed Sep 27 16:11:03 2017, Yoni Sher, Event acquisition pace for irregular timing 
    Reply  Mon Oct 2 16:08:05 2017, Stefan Ritt, Event acquisition pace for irregular timing 
Entry  Sun Aug 27 12:44:16 2017, Yuvaraj Elangovan, DRS4 version Support 
Entry  Fri Jul 21 09:16:02 2017, Volodymyr Rodin, Time output 
    Reply  Tue Jul 25 14:47:05 2017, Volodymyr Rodin, Time output 
Entry  Fri Jun 16 17:34:20 2017, Laura Gonella, Driver installation on Windows 10 
    Reply  Thu Jul 20 13:00:44 2017, Volodymyr Rodin, Driver installation on Windows 10 
Entry  Wed Jul 12 04:24:39 2017, Toshihiro Nonaka, Time resolution between boards 
    Reply  Wed Jul 12 20:16:05 2017, Stefan Ritt, Time resolution between boards 
Entry  Thu Jul 6 15:10:48 2017, Esperienza Giove, Trigger setting (AND AND) OR (AND AND) 
    Reply  Fri Jul 7 10:31:47 2017, Stefan Ritt, Trigger setting (AND AND) OR (AND AND) 
Entry  Thu Jun 8 14:26:23 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels 
    Reply  Thu Jun 8 15:52:20 2017, Stefan Ritt, AND Trigger problems with 2-3 channels 
       Reply  Fri Jun 9 09:44:33 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels Screenshot1.pngScreenshot2.pngScreenshot3.png
          Reply  Thu Jun 22 21:36:08 2017, Stefan Ritt, AND Trigger problems with 2-3 channels 
Entry  Tue May 30 20:45:30 2017, Esperienza Giove, Setting input range 
    Reply  Tue May 30 21:00:26 2017, Stefan Ritt, Setting input range 
       Reply  Tue May 30 21:22:10 2017, Esperienza Giove, Setting input range 
Entry  Mon May 22 18:27:56 2017, Esperienza Giove, Invalid magic number 0000 
    Reply  Tue May 23 10:24:47 2017, Stefan Ritt, Invalid magic number 0000 
       Reply  Thu May 25 20:17:41 2017, Esperienza Giove, Invalid magic number 0000 
          Reply  Fri May 26 08:48:25 2017, Stefan Ritt, Invalid magic number 0000 
       Reply  Thu May 25 20:20:57 2017, Esperienza Giove, Invalid magic number 0000 
Entry  Sat Apr 15 03:48:31 2017, Strahinja Lukic, Wave rotation during transfer from the board? 
    Reply  Wed Apr 19 12:17:25 2017, Stefan Ritt, Wave rotation during transfer from the board? 
       Reply  Thu Apr 20 06:30:13 2017, Strahinja Lukic, Wave rotation during transfer from the board? 
Entry  Thu Apr 13 16:42:21 2017, Christian Farina, Stand-alone Time Calibration for PSI Board 
    Reply  Thu Apr 13 16:50:18 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board 
       Reply  Thu Apr 13 16:54:32 2017, Christian Farina, Stand-alone Time Calibration for PSI Board 
          Reply  Thu Apr 13 17:02:01 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board 
             Reply  Thu Apr 13 17:10:58 2017, Christian Farina, Stand-alone Time Calibration for PSI Board 
Entry  Mon Apr 10 08:50:11 2017, Giovanni Bruni, drs4 registers behaviour 
    Reply  Mon Apr 10 10:50:57 2017, Stefan Ritt, drs4 registers behaviour 
       Reply  Mon Apr 10 13:41:41 2017, Giovanni Bruni, drs4 registers behaviour 
          Reply  Mon Apr 10 14:05:17 2017, Stefan Ritt, drs4 registers behaviour 
             Reply  Tue Apr 11 09:07:33 2017, Giovanni Bruni, drs4 registers behaviour 
                Reply  Tue Apr 11 09:41:44 2017, Stefan Ritt, drs4 registers behaviour 
Entry  Wed Apr 5 12:40:16 2017, Martin Petriska, DRS4 eval board v4 coincidence firmware changes for triger for short pulses 
    Reply  Mon Apr 10 10:48:03 2017, Stefan Ritt, DRS4 eval board v4 coincidence firmware changes for triger for short pulses 
Entry  Fri Feb 24 17:34:28 2017, Tarik Zengin, Passing parameters to drscl 
    Reply  Fri Feb 24 18:35:38 2017, Stefan Ritt, Passing parameters to drscl 
Entry  Tue Jan 31 01:37:35 2017, VO HONG HAI, LLD and ULD discriminations, 
    Reply  Tue Jan 31 08:40:04 2017, Stefan Ritt, LLD and ULD discriminations, 
Entry  Sat Jan 28 14:11:58 2017, Danny Petschke, AND trigger problems  
    Reply  Mon Jan 30 16:37:33 2017, Stefan Ritt, AND trigger problems  
Entry  Fri Jan 13 12:58:22 2017, Gregor Kramberger, DRS software doesn't work under Windows XP SP3 
    Reply  Fri Jan 13 13:16:09 2017, Stefan Ritt, DRS software doesn't work under Windows XP SP3 
    Reply  Fri Jan 13 13:50:10 2017, Stefan Ritt, DRS software doesn't work under Windows XP SP3 
Entry  Wed Nov 23 08:17:23 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data 
    Reply  Thu Nov 24 13:24:26 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data drs.pdf
       Reply  Tue Nov 29 23:19:06 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data 
          Reply  Wed Nov 30 08:53:58 2016, Stefan Ritt, Potential Incorrect Timing Calibration for DRS4 Data 
             Reply  Fri Dec 9 04:17:46 2016, Abhishek Rajput, Potential Incorrect Timing Calibration for DRS4 Data 
Entry  Wed Nov 30 17:48:39 2016, samridha kunwar, DRS4 Initiation 
    Reply  Wed Nov 30 19:05:24 2016, Stefan Ritt, DRS4 Initiation 
       Reply  Fri Dec 2 15:32:52 2016, samridha kunwar, DRS4 Initiation 
          Reply  Fri Dec 2 16:47:37 2016, Stefan Ritt, DRS4 Initiation 
Entry  Mon Nov 28 22:28:34 2016, Randall Gladen, Long timing between two channels 
    Reply  Wed Nov 30 10:45:29 2016, Stefan Ritt, Long timing between two channels 
Entry  Thu Nov 24 00:40:38 2016, Alexey Lubinets, PLL did not lock 
    Reply  Thu Nov 24 08:13:23 2016, Stefan Ritt, PLL did not lock 
       Reply  Mon Nov 28 16:48:15 2016, Alexey Lubinets, PLL did not lock 
          Reply  Mon Nov 28 16:52:38 2016, Stefan Ritt, PLL did not lock 
Entry  Fri Nov 18 05:52:45 2016, Kurtis Nishimura, Channel offsets in GetTime() offsetInstructions.png
    Reply  Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime() 
Entry  Wed Mar 9 09:57:20 2016, Christian D, LabView 
    Reply  Fri Nov 18 16:38:42 2016, Gerard Montarou, LabView 
Entry  Thu Nov 10 04:41:24 2016, Abhishek Rajput, Break Statements in DRS4 Binary to ROOT Macro 
    Reply  Thu Nov 10 09:56:04 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro 
       Reply  Thu Nov 10 19:24:52 2016, Abhishek Rajput, Break Statements in DRS4 Binary to ROOT Macro 
          Reply  Thu Nov 10 22:07:40 2016, Stefan Ritt, Break Statements in DRS4 Binary to ROOT Macro 
Entry  Fri Nov 4 17:41:03 2016, Christian Farina, Missing Header 
    Reply  Tue Nov 8 10:20:52 2016, Stefan Ritt, Missing Header 
       Reply  Wed Nov 9 17:19:48 2016, Christian Farina, Missing Header 
          Reply  Wed Nov 9 19:49:07 2016, Stefan Ritt, Missing Header 
             Reply  Thu Nov 10 20:54:45 2016, Christian Farina, Missing Header 
Entry  Wed Oct 26 21:15:35 2016, Alexey Lubinets, Problems with DRS command line 
    Reply  Thu Oct 27 08:29:26 2016, Stefan Ritt, Problems with DRS command line 
       Reply  Fri Oct 28 15:02:18 2016, Simon Mendisch, Problems with DRS command line 
          Reply  Fri Oct 28 15:51:59 2016, Stefan Ritt, Problems with DRS command line 
Entry  Tue Oct 11 22:11:26 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
Entry  Sun Oct 9 10:43:35 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
    Reply  Sun Oct 9 11:39:18 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
       Reply  Mon Oct 10 11:30:37 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s allChannels_zero_scaled.pngChn2_Chn3_1ns_delay_scaled.png
          Reply  Mon Oct 10 12:03:27 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s Screen_Shot_2016-10-10_at_12.01.03_.pngScreen_Shot_2016-10-10_at_12.01.57_.pngScreen_Shot_2016-10-10_at_12.36.48_.png
             Reply  Tue Oct 11 09:04:33 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
                Reply  Tue Oct 11 09:20:04 2016, Stefan Ritt, time difference between 2 channels only ~30-35ps @ 5GSmples/s 
Entry  Thu Oct 6 15:23:18 2016, Will Flanagan,  
Entry  Wed Oct 5 22:43:29 2016, Will Flanagan, Timestamp for each DRS4 waveform 
    Reply  Thu Oct 6 11:18:05 2016, Stefan Ritt, Timestamp for each DRS4 waveform 
Entry  Thu Sep 29 17:26:13 2016, Jacob Hwang, Output Timing Drifting Output_Drifting.jpg
    Reply  Fri Sep 30 17:03:38 2016, Stefan Ritt, Output Timing Drifting 
Entry  Mon Aug 29 09:36:34 2016, benjamin legeyt, increment write config register on the fly? 
    Reply  Mon Aug 29 10:57:33 2016, Stefan Ritt, increment write config register on the fly? 
       Reply  Mon Aug 29 12:18:49 2016, benjamin legeyt, increment write config register on the fly? 
          Reply  Mon Aug 29 12:51:48 2016, Stefan Ritt, increment write config register on the fly? 
Entry  Wed Jun 29 09:10:01 2016, Stefan Ritt, Negative input signals 
Entry  Sun Jun 12 08:45:52 2016, Michael, problems of DRS4 
    Reply  Wed Jun 15 14:49:00 2016, Stefan Ritt, problems of DRS4 
Entry  Sun Jun 12 08:49:54 2016, Michael, problems of DRS4 
Entry  Wed Jun 1 22:29:01 2016, Dominik Neise, problems when stop cell >= 767 ?? stop_cell_distribution.png
    Reply  Wed Jun 1 23:16:01 2016, Stefan Ritt, problems when stop cell >= 767 ?? 
Entry  Wed May 11 04:01:14 2016, Maksat, DRS4 Macro to save events 
    Reply  Thu May 12 12:38:17 2016, Stefan Ritt, DRS4 Macro to save events 
Entry  Thu May 12 05:18:47 2016, Yu, Problem For Software Download 
    Reply  Thu May 12 08:16:41 2016, Stefan Ritt, Problem For Software Download 
Entry  Wed May 11 15:48:57 2016, SANDJONG Saturnin Orly, Problme de Calibration de la DRS4 piedestaux_per_time.jpg
Entry  Mon Feb 29 13:33:06 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each 
    Reply  Mon Feb 29 14:09:21 2016, Stefan Ritt, two DRS4 boards configuration with 2048 samples each 
       Reply  Mon May 2 14:31:28 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each 
Entry  Thu Apr 28 15:47:53 2016, Stefan Ritt, New software version and binary format 
Entry  Wed Apr 27 20:04:12 2016, Abaz Kryemadhi, Best settings for time measurements 
    Reply  Thu Apr 28 15:46:34 2016, Stefan Ritt, Best settings for time measurements 
Entry  Wed Apr 27 08:14:14 2016, Toshihiro Nonaka, serial number problem  serial.png
    Reply  Wed Apr 27 09:04:01 2016, Stefan Ritt, serial number problem  
       Reply  Wed Apr 27 09:51:37 2016, Toshihiro Nonaka, serial number problem  
Entry  Fri Apr 15 12:58:46 2016, Konstantin Gusev, DRS4 purchase information 
    Reply  Tue Apr 26 13:42:42 2016, Stefan Ritt, DRS4 purchase information 
Entry  Thu Apr 21 22:16:43 2016, Kyle Weinfurther, Negative fCellDT values from GetTimeCalibration() ch5.pngch7.pngch9.png
    Reply  Sat Apr 23 12:33:17 2016, Daniel Stricker-Shaver, Negative fCellDT values from GetTimeCalibration() 
       Reply  Tue Apr 26 09:54:16 2016, Stefan Ritt, Negative fCellDT values from GetTimeCalibration() 
Entry  Mon Mar 21 10:38:27 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run  drs_settings.pngempty_drs.pngdrs_ofset.png
    Reply  Mon Apr 4 11:31:34 2016, Stefan Ritt, DRS Oscilloscope freezing after a long run  
       Reply  Mon Apr 4 11:41:26 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run  
          Reply  Mon Apr 4 12:08:15 2016, Stefan Ritt, DRS Oscilloscope freezing after a long run  
             Reply  Tue Apr 5 16:08:59 2016, Stefan Ritt, DRS Oscilloscope freezing after a long run  
                Reply  Wed Apr 6 08:41:08 2016, Stefan Ritt, DRS Oscilloscope freezing after a long run  Screen_Shot_2016-04-06_at_8.40.35_.png
                   Reply  Wed Apr 6 09:43:52 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run  
                Reply  Wed Apr 6 09:01:28 2016, Martin Petriska, DRS Oscilloscope freezing after a long run  
                   Reply  Wed Apr 6 09:46:10 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run  
Entry  Thu Mar 31 19:30:26 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal 
    Reply  Thu Mar 31 19:35:06 2016, Stefan Ritt, Trigger on the And of a positive and negative signal 
       Reply  Thu Mar 31 19:44:38 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal 
          Reply  Thu Mar 31 20:34:25 2016, Stefan Ritt, Trigger on the And of a positive and negative signal 
             Reply  Thu Mar 31 20:38:05 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal 
                Reply  Thu Mar 31 20:48:00 2016, Chris Thompson, Trigger on the And of a positive and negative signal 
                   Reply  Fri Apr 1 01:30:40 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal 
                      Reply  Fri Apr 1 22:09:07 2016, Chris Thompson, Trigger on the And of a positive and negative signal 
                         Reply  Sat Apr 2 17:22:34 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal 
                            Reply  Sun Apr 3 22:10:19 2016, Chris Thompson, Trigger on the And of a positive and negative signal Pulse_inverter.jpg
                               Reply  Sun Apr 3 22:34:28 2016, Abaz Kryemadhi, Trigger on the And of a positive and negative signal 
Entry  Sat Apr 2 11:21:10 2016, Felix Bachmair, Question about timimng calibration 
    Reply  Sat Apr 2 11:41:07 2016, Stefan Ritt, Question about timimng calibration 
Entry  Fri Mar 11 19:50:18 2016, Dominik Neise,  
    Reply  Tue Mar 22 12:54:41 2016, Stefan Ritt,  
Entry  Mon Feb 29 12:58:17 2016, Dmitry Philippov, baseline shift pic1.pngpic2.pngpic3.png
    Reply  Mon Feb 29 13:09:29 2016, Stefan Ritt, baseline shift 
Entry  Thu Nov 26 18:59:27 2015, Robert Adams, Saving histogram data 
    Reply  Tue Feb 16 11:21:43 2016, Stefan Ritt, Saving histogram data 
    Reply  Tue Feb 16 11:55:54 2016, Martin Petriska, Saving histogram data 
Entry  Thu Jan 14 21:49:37 2016, Chris Thompson, Triggering of DRS4 in the fastest sampling mode OR_mode_selected.jpgAND_mode_selected.jpg20ns_per_div.jpg
    Reply  Fri Jan 15 08:09:00 2016, Stefan Ritt, Triggering of DRS4 in the fastest sampling mode edge.png
Entry  Wed Dec 23 15:38:14 2015, mony orbach, Dtap stops toggling after 40msec 
    Reply  Wed Dec 23 15:48:42 2015, Stefan Ritt, Dtap stops toggling after 40msec 
       Reply  Thu Dec 24 10:51:31 2015, mony orbach, Dtap stops toggling after 40msec 
          Reply  Thu Dec 24 12:45:41 2015, Stefan Ritt, Dtap stops toggling after 40msec 
             Reply  Sun Dec 27 15:41:32 2015, mony orbach, Dtap stops toggling after 40msec Dtap-Denable.gifdtap-Danable2.gifDtap-refck.gifDtap-Dspeed.gif
                Reply  Mon Dec 28 11:05:15 2015, Stefan Ritt, Dtap stops toggling after 40msec 
                   Reply  Mon Dec 28 11:21:54 2015, mony orbach, Dtap stops toggling after 40msec 
                      Reply  Wed Dec 30 16:25:35 2015, mony orbach, Dtap stops toggling after 40msec 
                         Reply  Wed Dec 30 17:00:00 2015, Stefan Ritt, Dtap stops toggling after 40msec 
                            Reply  Thu Jan 14 14:00:26 2016, mony orbach, Dtap stops toggling after 40msec 
                               Reply  Thu Jan 14 14:11:06 2016, Stefan Ritt, Dtap stops toggling after 40msec 
Entry  Tue Jan 12 17:57:03 2016, Jack Bargemann, Compiling DRS-exam 
    Reply  Tue Jan 12 21:02:31 2016, Stefan Ritt, Compiling DRS-exam 
Entry  Wed Jan 6 15:51:58 2016, Larry Byars, Use of Channel Cascading in drs_exam.cpp 
    Reply  Tue Jan 12 15:42:31 2016, Larry Byars, Use of Channel Cascading in drs_exam.cpp 
       Reply  Tue Jan 12 16:06:07 2016, Stefan Ritt, Use of Channel Cascading in drs_exam.cpp 
Entry  Wed Nov 25 02:52:35 2015, Chris Thompson, PC software beyond Windows 7 
    Reply  Wed Nov 25 08:20:47 2015, Stefan Ritt, PC software beyond Windows 7 
       Reply  Wed Nov 25 17:36:25 2015, Chris Thompson, PC software beyond Windows 7 Installation_failure_screen.jpg
          Reply  Sat Dec 5 02:39:20 2015, Chris Thompson, PC software beyond Windows 7 
             Reply  Sat Dec 5 03:21:21 2015, Chris Thompson, PC software beyond Windows 7 
                Reply  Tue Jan 12 12:57:46 2016, Stefan Ritt, PC software beyond Windows 7 
Entry  Tue Nov 3 22:37:56 2015, Will Flanagan, Latest macro for DRS4 V5 
    Reply  Tue Nov 3 23:15:38 2015, Will Flanagan, Latest macro for DRS4 V5 
    Reply  Wed Nov 4 15:40:10 2015, Stefan Ritt, Latest macro for DRS4 V5 
       Reply  Thu Nov 5 00:18:42 2015, Will Flanagan, Latest macro for DRS4 V5 
Entry  Wed Oct 7 13:06:34 2015, Ilja Bekman, Voltage Calibration with signal on the input 
Entry  Wed Aug 19 15:07:53 2015, Martin Petriska, QtPALS 
Entry  Fri Aug 7 18:41:37 2015, dante, DRS4 
    Reply  Fri Aug 7 20:32:15 2015, Felix Bachmair, DRS4 
Entry  Mon Jul 20 09:25:38 2015, Chenfei Yang, Measure the time between different samples 
    Reply  Thu Jul 23 13:46:12 2015, Stefan Ritt, Measure the time between different samples 
Entry  Thu Jul 2 13:20:51 2015, Felix Bachmair, Creation of Object files 
    Reply  Fri Jul 3 17:13:27 2015, Stefan Ritt, Creation of Object files 
       Reply  Mon Jul 6 11:30:56 2015, Felix Bachmair, Creation of Object files 
          Reply  Mon Jul 6 19:25:27 2015, Stefan Ritt, Creation of Object files 
             Reply  Tue Jul 7 09:29:21 2015, Felix Bachmair, Creation of Object files Makefile
Entry  Sat May 23 11:03:20 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz drs_v5_newStefan_10Hz.pngdrs_v5_newStefan_4Hz.pngdrs_v5_500_160Hz.pngdrs_5-0-0_4hz.png
    Reply  Thu Jul 2 08:53:17 2015, Felix Bachmair, Issue with Trigger rates below ~100Hz 
Entry  Thu Jun 18 17:33:05 2015, Gregor Kramberger, drs 5.03 and windows 8.1 
    Reply  Fri Jun 19 12:32:10 2015, Gregor Kramberger, drs 5.03 and windows 8.1 
Entry  Tue Jun 16 20:45:54 2015, Michael Buadelk, DRS4 Evaluation Board Osc Application 
    Reply  Tue Jun 16 22:26:41 2015, Stefan Ritt, DRS4 Evaluation Board Osc Application 
Entry  Tue May 19 14:14:45 2015, Ilja Bekman, DRS4 firmware UCF constraints  
    Reply  Fri May 22 14:25:45 2015, Stefan Ritt, DRS4 firmware UCF constraints  firmware.zip
       Reply  Tue May 26 11:27:27 2015, Felix Bachmair, DRS4 firmware UCF constraints  
          Reply  Fri Jun 5 12:07:38 2015, Stefan Ritt, DRS4 firmware UCF constraints  
             Reply  Fri Jun 5 13:15:35 2015, Felix Bachmair, DRS4 firmware UCF constraints  
                Reply  Fri Jun 5 13:29:55 2015, Stefan Ritt, DRS4 firmware UCF constraints  
                   Reply  Fri Jun 5 13:32:03 2015, Stefan Ritt, DRS4 firmware UCF constraints  
Entry  Sun May 24 09:34:27 2015, Peter Steinberg, Peculiar behavior of time values for Rev5 DRS4 EB 
    Reply  Wed Jun 3 09:07:38 2015, Stefan Ritt, Peculiar behavior of time values for Rev5 DRS4 EB 
Entry  Wed May 13 09:31:18 2015, Chenfei Yang, transparent-mode voltage tek00000_.png
    Reply  Wed May 13 09:45:51 2015, Stefan Ritt, transparent-mode voltage 
       Reply  Wed May 13 09:55:09 2015, Chenfei Yang, transparent-mode voltage 
          Reply  Wed May 13 10:16:40 2015, Stefan Ritt, transparent-mode voltage 
             Reply  Wed May 13 10:27:43 2015, Chenfei Yang, transparent-mode voltage 
             Reply  Wed May 13 12:34:49 2015, Stefan Ritt, transparent-mode voltage 
                Reply  Wed May 13 12:52:22 2015, Chenfei Yang, transparent-mode voltage 
                Reply  Wed May 13 16:13:07 2015, Chenfei Yang, transparent-mode voltage 
                   Reply  Wed May 13 16:25:24 2015, Stefan Ritt, transparent-mode voltage 
Entry  Wed May 13 00:52:51 2015, Cosmin Deaconu, Getting Trigger Source 
    Reply  Wed May 13 08:19:53 2015, Stefan Ritt, Getting Trigger Source 
Entry  Wed May 13 01:07:36 2015, Cosmin Deaconu, DRS4 Evaluation Board + Powered USB Hub 
Entry  Sun Apr 5 22:16:48 2015, Julien Wulf, DRS4 Evaluation Board Baseline/Voltage Calibration  
    Reply  Tue Apr 21 12:52:18 2015, Stefan Ritt, DRS4 Evaluation Board Baseline/Voltage Calibration  
       Reply  Tue Apr 21 13:03:38 2015, Daniel Stricker-Shaver, DRS4 Evaluation Board Baseline/Voltage Calibration  
          Reply  Tue Apr 21 13:06:39 2015, Stefan Ritt, DRS4 Evaluation Board Baseline/Voltage Calibration  
Entry  Thu Apr 9 11:46:33 2015, Felix Bachmair, DRSBoard::SetTriggerSource 
    Reply  Tue Apr 21 12:01:45 2015, Stefan Ritt, DRSBoard::SetTriggerSource 
Entry  Wed Oct 15 10:14:32 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
    Reply  Wed Oct 15 10:52:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ 
       Reply  Wed Oct 15 11:34:43 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
       Reply  Wed Oct 15 12:15:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ drs_exam_multi.cpp
          Reply  Fri Apr 17 10:07:38 2015, Simon Weingarten, Clock settings in daisy chain DAQ 
             Reply  Mon Apr 20 13:08:24 2015, Stefan Ritt, Clock settings in daisy chain DAQ 
Entry  Mon Mar 16 16:07:39 2015, Hermann-Josef Mathes, Running 2 instances of a DRS DAQ program 
    Reply  Tue Mar 17 02:53:26 2015, Stefan Ritt, Running 2 instances of a DRS DAQ program 
       Reply  Thu Mar 19 07:37:52 2015, Daniel Stricker-Shaver, Running 2 instances of a DRS DAQ program 
Entry  Fri Feb 13 10:12:16 2015, Andrzej Grzeszczuk, drs4 and root 
Entry  Fri Jan 16 13:29:05 2015, Rainer Hentges, Mac OSX Yosemite 10.10 
    Reply  Fri Jan 16 14:12:19 2015, Stefan Ritt, Mac OSX Yosemite 10.10 
Entry  Mon Nov 17 16:36:18 2014, Mickey Chiu, Raspberry Pi drsosc does not exit properly 
    Reply  Tue Nov 25 14:06:34 2014, Stefan Ritt, Raspberry Pi drsosc does not exit properly 
Entry  Sun Oct 19 14:36:54 2014, Chris Tully, coverting the xml file format into binary 
Entry  Wed Aug 13 20:17:19 2014, Roman Gredig, binary files time calibration header in drs-5.0.2 
    Reply  Thu Oct 16 16:16:12 2014, Stefan Ritt, binary files time calibration header in drs-5.0.2 
Entry  Tue Aug 26 14:16:26 2014, Roman Gredig, binary files with more than 4 drs board ver. 5.0.2 
    Reply  Thu Oct 16 16:15:16 2014, Stefan Ritt, binary files with more than 4 drs board ver. 5.0.2 
Entry  Tue Oct 7 14:09:02 2014, Stephane Debieux, USB Microcontroller firmware 
    Reply  Mon Oct 13 16:46:56 2014, Stefan Ritt, USB Microcontroller firmware 
       Reply  Mon Oct 13 17:08:40 2014, Stephane Debieux, USB Microcontroller firmware 
          Reply  Mon Oct 13 17:14:58 2014, Stefan Ritt, USB Microcontroller firmware 
             Reply  Tue Oct 14 16:21:07 2014, Stephane Debieux, USB Microcontroller firmware 
                Reply  Tue Oct 14 16:29:12 2014, Stefan Ritt, USB Microcontroller firmware 
                   Reply  Tue Oct 14 16:34:45 2014, Stephane Debieux, USB Microcontroller firmware 
                      Reply  Tue Oct 14 16:38:14 2014, Stefan Ritt, USB Microcontroller firmware 
                         Reply  Tue Oct 14 16:51:37 2014, Stephane Debieux, USB Microcontroller firmware 
Entry  Mon Sep 15 16:24:41 2014, Hannes Wachter, Timing Calibration Fail 
    Reply  Mon Sep 22 15:04:37 2014, Stefan Ritt, Timing Calibration Fail 
Entry  Fri Sep 12 14:57:22 2014, Dmitry Hits, compilation error for v5.0.2 
    Reply  Fri Sep 12 16:08:49 2014, Stefan Ritt, compilation error for v5.0.2 
       Reply  Fri Sep 12 16:38:24 2014, Dmitry Hits, compilation error for v5.0.2 
          Reply  Mon Sep 22 14:52:21 2014, Stefan Ritt, compilation error for v5.0.2 
Entry  Fri Sep 12 11:52:21 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer 
    Reply  Fri Sep 12 13:00:04 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer 
       Reply  Fri Sep 12 13:37:42 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer 
          Reply  Fri Sep 12 13:41:43 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer 
Entry  Thu Aug 21 11:03:36 2014, Martin Petriska, 10GSps on DRS4 Evm with delay cables 
    Reply  Tue Aug 26 12:32:21 2014, Stefan Ritt, 10GSps on DRS4 Evm with delay cables 
Entry  Tue May 13 19:34:58 2014, Luka Pavelic, drsosc binary to cern ROOT file conversion 
    Reply  Tue May 13 19:39:36 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion 
       Reply  Tue May 13 22:03:47 2014, Luka Pavelic, drsosc binary to cern ROOT file conversion 
          Reply  Tue May 13 23:08:50 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion 
             Reply  Fri Jun 27 11:23:19 2014, ChengMing Du, drsosc binary to cern ROOT file conversion 
                Reply  Wed Jul 30 17:05:38 2014, Stefan Ritt, drsosc binary to cern ROOT file conversion 
Entry  Tue Jun 18 14:19:39 2013, Stefan Ritt, ROOT program to decode binary data from DRSOsc decode.Cc1.gif
    Reply  Wed Jul 30 17:05:06 2014, Stefan Ritt, ROOT program to decode binary data from DRSOsc read_binary.Cread_binary.cpp
Entry  Wed Jul 30 11:38:58 2014, Tsutomu Nagayoshi, Sampling speed of DRS4 Board ver4 
Entry  Mon Jul 14 19:03:05 2014, Yves Bianga, change cascading from 1024 to 2048 bins for each input channel 
    Reply  Wed Jul 16 12:10:19 2014, Stefan Ritt, change cascading from 1024 to 2048 bins for each input channel 
Entry  Wed Jan 15 14:20:51 2014, Stefan Ritt, Announcement of new Evaluation Board V5 drsosc.png
    Reply  Tue Feb 18 14:12:37 2014, Stefan Ritt, Announcement of new Evaluation Board V5 scope.png
       Reply  Mon Jun 9 12:03:26 2014, Osip Lishilin, Announcement of new Evaluation Board V5 
          Reply  Wed Jun 11 11:13:50 2014, Stefan Ritt, Announcement of new Evaluation Board V5 
             Reply  Mon Jun 16 15:35:59 2014, Osip Lishilin, Announcement of new Evaluation Board V5 
Entry  Thu May 29 04:22:43 2014, Toshihiro Nonaka, CalibrationWaveform offset.png
    Reply  Thu Jun 12 17:16:13 2014, Stefan Ritt, CalibrationWaveform 
Entry  Thu Jun 12 12:40:03 2014, Roman Gredig, DRS eval bord v5 Timing eqn1.png
    Reply  Thu Jun 12 12:46:00 2014, Stefan Ritt, DRS eval bord v5 Timing 
Entry  Tue May 27 13:46:18 2014, Dominik Neise, Spikes in DRS4 data on custom baord. 
    Reply  Tue May 27 16:07:17 2014, Stefan Ritt, Spikes in DRS4 data on custom baord. 
Entry  Fri May 16 14:04:47 2014, Benjamin LeGeyt, simultaneous writing and reading with region of interest mode? 
    Reply  Mon May 19 08:04:57 2014, Stefan Ritt, simultaneous writing and reading with region of interest mode? 
Entry  Tue Apr 15 18:35:41 2014, Carlo Stella, drs_exam project fail to compile 
    Reply  Wed Apr 16 08:20:36 2014, Stefan Ritt, drs_exam project fail to compile 
       Reply  Thu Apr 24 23:03:25 2014, Carlo Stella, drs_exam project fail to compile 
Entry  Thu Apr 17 12:02:28 2014, Wang , The first channel is wrong. QQ??20140417174309.jpg
Entry  Thu Apr 10 14:45:12 2014, Roman Gredig, DRS4 Evalboard V5 with Windows7Pro64bit 
    Reply  Wed Apr 16 10:24:55 2014, Stefan Ritt, DRS4 Evalboard V5 with Windows7Pro64bit 
Entry  Wed Apr 16 03:22:43 2014, Wang , why is the first channel output error?  QQ??20140416090124.jpg
    Reply  Wed Apr 16 08:30:32 2014, Stefan Ritt, why is the first channel output error?  
Entry  Wed Mar 5 21:54:13 2014, Hermann-Josef Mathes, Software drs-5.0.0 fails to compile (drsosc) drs-5.patch
    Reply  Thu Mar 6 11:12:44 2014, Stefan Ritt, Software drs-5.0.0 fails to compile (drsosc) 
Entry  Wed Aug 7 15:05:59 2013, Hermann-Josef Mathes, Repeated time calibration 
    Reply  Wed Aug 7 15:10:57 2013, Stefan Ritt, Repeated time calibration 
       Reply  Wed Aug 7 15:20:33 2013, Hermann-Josef Mathes, Repeated time calibration 
          Reply  Wed Feb 5 13:41:42 2014, Stefan Ritt, Repeated time calibration 
Entry  Wed May 8 06:07:52 2013, Andrey Kuznetsov, DRS4 v2.0 Eval Board running on higher versions of DRS Oscilloscope program 
    Reply  Wed May 8 19:50:01 2013, Andrey Kuznetsov, DRS4 installation on Windows 8 issues 
       Reply  Wed Jan 15 17:37:21 2014, Stefan Ritt, DRS4 installation on Windows 8 issues 
    Reply  Wed Jan 15 17:34:55 2014, Stefan Ritt, DRS4 v2.0 Eval Board running on higher versions of DRS Oscilloscope program 
Entry  Wed Aug 28 13:07:51 2013, Andrey Kuznetsov, Some bug fixes and questions 
    Reply  Thu Sep 5 10:01:00 2013, Andrey Kuznetsov, Some bug fixes and questions 
       Reply  Mon Sep 9 06:49:36 2013, Andrey Kuznetsov, Some bug fixes and questions 
          Reply  Wed Jan 15 17:11:14 2014, Stefan Ritt, Some bug fixes and questions 
       Reply  Wed Jan 15 17:02:58 2014, Stefan Ritt, Some bug fixes and questions 
    Reply  Wed Jan 15 16:15:00 2014, Stefan Ritt, Some bug fixes and questions 
Entry  Tue Sep 10 10:31:30 2013, Akira Okumura, USB connection stops drs_simple.cpp
    Reply  Wed Sep 11 02:41:28 2013, Andrey Kuznetsov, USB connection stops 
       Reply  Wed Sep 25 14:42:00 2013, Akira Okumura, USB connection stops 
    Reply  Wed Jan 15 15:48:55 2014, Stefan Ritt, USB connection stops 
Entry  Thu Jan 9 10:58:19 2014, Martin Petriska, v5 software with v4 board calibration 
    Reply  Thu Jan 9 11:02:46 2014, Stefan Ritt, v5 software with v4 board calibration 
Entry  Mon Nov 18 15:49:01 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis 
    Reply  Mon Nov 18 16:00:26 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis 
       Reply  Mon Dec 16 11:09:25 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis 
          Reply  Tue Dec 17 08:45:32 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis 
Entry  Fri Dec 13 10:37:18 2013, Dmitry Hits, input protection in DRS4 evaluation board 
    Reply  Fri Dec 13 11:37:58 2013, Stefan Ritt, input protection in DRS4 evaluation board 
Entry  Tue Dec 10 14:48:42 2013, ismail okan atakisi, measurement range 
    Reply  Tue Dec 10 14:54:46 2013, Stefan Ritt, measurement range 
Entry  Tue Nov 26 15:36:39 2013, Dmitry Hits, reducing sampling speed 
    Reply  Tue Nov 26 15:38:13 2013, Stefan Ritt, reducing sampling speed 
Entry  Thu Nov 14 11:39:06 2013, Schablo, Cascading of channels  
    Reply  Thu Nov 14 12:51:56 2013, Stefan Ritt, Cascading of channels  2048_mode.pdf
       Reply  Thu Nov 21 14:35:57 2013, Schablo, Cascading of channels  
          Reply  Thu Nov 21 14:45:56 2013, Stefan Ritt, Cascading of channels  
Entry  Tue Nov 19 04:33:22 2013, Andriy Zatserklyaniy, DRSOsc at Mac OS X Mavericks 
    Reply  Tue Nov 19 09:09:01 2013, Stefan Ritt, DRSOsc at Mac OS X Mavericks 
       Reply  Tue Nov 19 21:49:37 2013, Andriy Zatserklyaniy, DRSOsc at Mac OS X Mavericks 
          Reply  Wed Nov 20 08:16:10 2013, Stefan Ritt, DRSOsc at Mac OS X Mavericks 
Entry  Wed Nov 6 11:53:28 2013, Dmitry Hits, flickering screen for drsosc 
    Reply  Wed Nov 6 12:25:31 2013, Stefan Ritt, flickering screen for drsosc 
       Reply  Mon Nov 18 11:20:15 2013, Dmitry Hits, flickering screen for drsosc 
Entry  Tue Aug 27 16:14:49 2013, lengchongyang,  
    Reply  Wed Aug 28 04:05:48 2013, lengchongyang,  
       Reply  Wed Nov 6 16:35:42 2013, Stefan Ritt,  
Entry  Mon Oct 21 14:43:21 2013, Stephane Debieux, DRS4 analog outputs - interfacing DRS4 to AD9222 ADC 
Entry  Mon Sep 23 09:22:52 2013, Andrzej Rychter, Sampling Frequency: DRS4 eval board 
    Reply  Mon Sep 23 09:26:56 2013, Stefan Ritt, Sampling Frequency: DRS4 eval board 
       Reply  Mon Sep 23 09:51:48 2013, Andrzej Rychter, Sampling Frequency: DRS4 eval board 
Entry  Sun May 26 13:08:52 2013, tmiron alon,  
    Reply  Fri Jun 7 10:22:48 2013, Stefan Ritt,  
       Reply  Fri Jun 7 11:44:17 2013, tmiron alon, thank you 
       Reply  Mon Jun 10 14:09:13 2013, tmiron alon, add an average ability to the Scope 
          Reply  Mon Jun 10 16:24:21 2013, Stefan Ritt, add an average ability to the Scope 
             Reply  Thu Jul 4 08:32:11 2013, tmiron alon, add an average ability to the Scope 
                Reply  Thu Jul 4 08:54:25 2013, Stefan Ritt, add an average ability to the Scope 
                   Reply  Thu Jul 4 09:07:24 2013, tmiron alon, add an average ability to the Scope 
                      Reply  Thu Jul 4 09:17:31 2013, Stefan Ritt, add an average ability to the Scope 
                         Reply  Thu Jul 4 10:01:06 2013, tmiron alon, add an average ability to the Scope 
                            Reply  Thu Jul 4 10:14:32 2013, Stefan Ritt, add an average ability to the Scope 
                               Reply  Tue Jul 16 10:02:28 2013, tmiron alon, add an average ability to the Scope 
                                  Reply  Tue Jul 16 16:25:43 2013, Stefan Ritt, add an average ability to the Scope 
                                     Reply  Sun Jul 28 09:52:25 2013, tmiron alon, add an average ability to the Scope 
                                        Reply  Mon Jul 29 06:04:45 2013, Stefan Ritt, add an average ability to the Scope 
                                           Reply  Mon Aug 12 15:08:17 2013, tmiron alon, add an average ability to the Scope 
                                              Reply  Mon Aug 12 22:18:39 2013, Stefan Ritt, add an average ability to the Scope 
Entry  Tue Jul 23 22:31:08 2013, alonzi, Evaluation Board Behavior Screenshot.pngdata_problem.png
    Reply  Tue Jul 23 22:35:08 2013, Stefan Ritt, Evaluation Board Behavior 
       Reply  Tue Jul 23 22:42:31 2013, alonzi, Evaluation Board Behavior 
          Reply  Thu Jul 25 01:31:29 2013, Andrey Kuznetsov, Evaluation Board Behavior 
Entry  Tue Jul 9 11:40:00 2013, Dmitry Hits, cannot save in binary format 
    Reply  Tue Jul 9 12:23:06 2013, Stefan Ritt, cannot save in binary format 
       Reply  Tue Jul 9 14:00:49 2013, Dmitry Hits, cannot save in binary format 
Entry  Fri Jul 5 12:46:45 2013, Hermann-Josef Mathes, Missing methods in drs-4.0.1.tar.gz 
    Reply  Sat Jul 6 06:10:38 2013, Stefan Ritt, Missing methods in drs-4.0.1.tar.gz 
Entry  Wed Feb 22 11:36:51 2012, sonal, DRS4- analog pulse counting 
    Reply  Fri Feb 24 15:52:43 2012, Stefan Ritt, DRS4- analog pulse counting 
       Reply  Wed Feb 29 06:46:47 2012, Sonal, DRS4- analog pulse counting 
          Reply  Thu Mar 1 19:22:26 2012, Stefan Ritt, DRS4- analog pulse counting 
             Reply  Wed Mar 6 12:35:38 2013, Osip Lishilin, DRS4- analog pulse counting 
                Reply  Wed Mar 6 12:37:14 2013, Stefan Ritt, DRS4- analog pulse counting 
                   Reply  Mon May 20 08:42:16 2013, Osip Lishilin, DRS4- analog pulse counting 
                      Reply  Sat May 25 21:03:22 2013, Stefan Ritt, DRS4- analog pulse counting 
Entry  Tue May 21 12:39:00 2013, Enrico Conti, mac osx 10.6 
    Reply  Tue May 21 13:25:41 2013, Stefan Ritt, mac osx 10.6 
       Reply  Tue May 21 17:45:05 2013, Enrico Conti, mac osx 10.6 
    Reply  Tue May 21 13:32:13 2013, Martin Petriska, mac osx 10.6 
       Reply  Tue May 21 17:48:45 2013, Enrico Conti, mac osx 10.6 
          Reply  Tue May 21 17:51:09 2013, Stefan Ritt, mac osx 10.6 
             Reply  Tue May 21 18:30:11 2013, Enrico Conti, mac osx 10.6 
             Reply  Fri May 24 17:58:07 2013, Enrico Conti, mac osx 10.6 
                Reply  Fri May 24 18:20:14 2013, Stefan Ritt, mac osx 10.6 
                   Reply  Sat May 25 12:45:46 2013, Enrico Conti, mac osx 10.6 
Entry  Mon Apr 22 15:33:28 2013, Benjamin LeGeyt, effect of jitter/alignment between SRCLK and ADC clock 
    Reply  Mon Apr 22 15:52:53 2013, Stefan Ritt, effect of jitter/alignment between SRCLK and ADC clock adc_phase.jpg
Entry  Thu Apr 11 22:41:13 2013, Bill Ashmanskas, code/details for optimal DRS4 timing calibration? tcalib.png
    Reply  Fri Apr 12 08:38:17 2013, Stefan Ritt, code/details for optimal DRS4 timing calibration? 
Entry  Mon Apr 8 18:11:02 2013, Dmitry Hits, binary to root 
Entry  Mon Mar 25 11:12:53 2013, Georg Winner, Differences in Source Code 
    Reply  Thu Apr 4 11:21:04 2013, Stefan Ritt, Differences in Source Code 
Entry  Wed Feb 27 13:47:32 2013, Georg Winner, Chip Test - Cell Error 
    Reply  Wed Mar 6 13:08:03 2013, Stefan Ritt, Chip Test - Cell Error 
Entry  Thu Feb 28 10:47:14 2013, Dmitry Hits, clock and trigger outs 
    Reply  Thu Feb 28 12:58:44 2013, Stefan Ritt, clock and trigger outs 
Entry  Fri Feb 22 11:46:17 2013, Yury Golod, DRS4 trigger, different polarity 
    Reply  Fri Feb 22 11:56:57 2013, Stefan Ritt, DRS4 trigger, different polarity 
Entry  Wed Feb 13 16:58:40 2013, Martin Petriska, Nonuniform sampling 
    Reply  Wed Feb 13 17:03:53 2013, Stefan Ritt, Nonuniform sampling 
Entry  Thu Dec 27 00:12:12 2012, Jinhong Wang, variation of sampling capacitors 
    Reply  Thu Dec 27 09:49:17 2012, Stefan Ritt, variation of sampling capacitors 
       Reply  Thu Dec 27 18:15:14 2012, Jinhong Wang, variation of sampling capacitors 
          Reply  Fri Feb 1 17:43:48 2013, Jinhong Wang, variation of sampling capacitors 
             Reply  Tue Feb 5 14:38:35 2013, Stefan Ritt, variation of sampling capacitors 
Entry  Thu Dec 6 09:23:36 2012, Martin Petriska, EVM rev4 board trigger change and drs_example 
    Reply  Fri Dec 14 21:49:29 2012, Stefan Ritt, EVM rev4 board trigger change and drs_example 
Entry  Thu Dec 13 12:03:29 2012, Evgeni, DRS-4 trigger 
    Reply  Thu Dec 13 12:14:35 2012, Stefan Ritt, DRS-4 trigger 
       Reply  Thu Dec 13 19:49:47 2012, Evgeni, DRS-4 trigger 
          Reply  Fri Dec 14 08:42:53 2012, Stefan Ritt, DRS-4 trigger DRSOsc.png
             Reply  Fri Dec 14 10:07:54 2012, Evgeni, DRS-4 trigger 
    Reply  Fri Dec 14 10:07:14 2012, Evgeni, DRS-4 trigger 
Entry  Tue Dec 4 09:24:22 2012, Zhongwei Du, Question of drs4 using 
    Reply  Tue Dec 4 09:39:44 2012, Stefan Ritt, Question of drs4 using 
       Reply  Tue Dec 4 09:50:11 2012, Zhongwei Du, Question of drs4 using 
          Reply  Tue Dec 4 09:55:43 2012, Stefan Ritt, Question of drs4 using 
Entry  Mon Dec 3 08:32:28 2012, Gyuhee Kim, Another question about using multi boards. 
    Reply  Mon Dec 3 09:18:09 2012, Stefan Ritt, Another question about using multi boards. 
       Reply  Mon Dec 3 11:40:35 2012, Gyuhee Kim, Another question about using multi boards. 
Entry  Wed Nov 28 16:54:46 2012, Stefan Ritt, DRS Oscilloscope for Raspberry Pi and Mac OSX 10.8 screenshot_pi.png
Entry  Wed Nov 21 08:34:52 2012, Gyuhee Kim, Question for using Multi board 
    Reply  Wed Nov 21 08:38:26 2012, Stefan Ritt, Question for using Multi board 
       Reply  Wed Nov 21 08:48:00 2012, Gyuhee Kim, Question for using Multi board 
Entry  Mon Oct 29 18:30:28 2012, Martin Petriska, GetWave 
    Reply  Tue Nov 13 11:26:32 2012, Stefan Ritt, GetWave 
Entry  Thu Nov 1 20:08:33 2012, hongwei yang, DRS4 firmware 
    Reply  Thu Nov 1 20:17:42 2012, Stefan Ritt, DRS4 firmware drs4_eval4_app.vhd
       Reply  Thu Nov 1 20:21:44 2012, hongwei yang, DRS4 firmware 
          Reply  Thu Nov 1 20:25:53 2012, hongwei yang, DRS4 firmware 
             Reply  Thu Nov 1 20:32:03 2012, Stefan Ritt, DRS4 firmware drs4_eval4.vhd
                Reply  Thu Nov 1 20:46:53 2012, hongwei yang, DRS4 firmware 
Entry  Fri Oct 12 14:06:04 2012, Moritz von Witzleben, DRS abbreviation 
    Reply  Fri Oct 12 14:09:37 2012, Stefan Ritt, DRS abbreviation 
Entry  Thu Oct 4 20:50:36 2012, Zach Miller, DRS5 
    Reply  Thu Oct 4 20:59:18 2012, Stefan Ritt, DRS5 
       Reply  Thu Oct 4 21:07:27 2012, Zach Miller, DRS5 
Entry  Tue Aug 28 17:52:45 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 
    Reply  Wed Aug 29 10:52:44 2012, Stefan Ritt, DRS-4.0.0 DOScreen.cpp 
       Reply  Wed Aug 29 16:42:42 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 
          Reply  Wed Aug 29 16:45:36 2012, Stefan Ritt, DRS-4.0.0 DOScreen.cpp 
             Reply  Wed Aug 29 16:57:49 2012, Zach Miller, DRS-4.0.0 DOScreen.cpp 
Entry  Wed Aug 1 17:42:32 2012, Mayank S. Rajguru, Calculation of loop filter parameters (R,C1and C1) for 1 GHz 
    Reply  Mon Aug 6 02:44:00 2012, Stefan Ritt, Calculation of loop filter parameters (R,C1and C1) for 1 GHz 
Entry  Mon Jul 9 14:14:48 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows compile_log.txt
    Reply  Tue Jul 10 13:15:00 2012, Stefan Ritt, Problem compiling drs_exam.cpp on windows 
       Reply  Wed Jul 11 10:04:51 2012, Ivan Petrov, Problem compiling drs_exam.cpp on windows 
Entry  Tue Mar 20 16:23:33 2012, Martin Petriska, triger for measuring time between pulses in channels 
    Reply  Tue Mar 20 16:33:50 2012, Stefan Ritt, triger for measuring time between pulses in channels 
       Reply  Wed Mar 21 09:33:00 2012, Martin Petriska, triger for measuring time between pulses in channels 
          Reply  Wed Mar 21 09:39:33 2012, Stefan Ritt, triger for measuring time between pulses in channels 
             Reply  Wed Jun 20 10:40:21 2012, Ivan Petrov, triger for measuring time between pulses in channels 
                Reply  Wed Jun 20 12:45:05 2012, Stefan Ritt, triger for measuring time between pulses in channels 
                   Reply  Wed Jun 20 14:36:01 2012, Ivan Petrov, triger for measuring time between pulses in channels 
                      Reply  Wed Jun 20 14:44:38 2012, Stefan Ritt, triger for measuring time between pulses in channels 
                         Reply  Sat Jun 23 00:29:52 2012, Andrey Kuznetsov, triger for measuring time between pulses in channels 
                            Reply  Mon Jun 25 14:21:13 2012, Stefan Ritt, triger for measuring time between pulses in channels 
Entry  Mon Apr 23 10:38:51 2012, Guillaume Blanchard, DRS4 Initialization 
    Reply  Wed Apr 25 13:42:37 2012, Stefan Ritt, DRS4 Initialization 
Entry  Wed Feb 15 18:08:13 2012, Yuji Iwai, Evaluation Board v4 Trigger/Clock Connectors 
Entry  Sat Feb 4 11:59:26 2012, Zhongwei Du, what sort of detectors for physical experiment the DRS4 used? 
    Reply  Mon Feb 6 08:15:38 2012, Stefan Ritt, what sort of detectors for physical experiment the DRS4 used? 
Entry  Tue Jan 31 08:10:37 2012, Stefan Ritt, IEEE Real Time 2012 Call for Abstracts 
Entry  Thu Jan 26 09:12:03 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting 
    Reply  Thu Jan 26 09:15:42 2012, Stefan Ritt, DRS4 Rev2.0 for analog pulse counting 
       Reply  Thu Jan 26 09:44:34 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting 
          Reply  Thu Jan 26 09:49:38 2012, Stefan Ritt, DRS4 Rev2.0 for analog pulse counting 
             Reply  Thu Jan 26 10:05:57 2012, Ravindra Raghunath Shinde, DRS4 Rev2.0 for analog pulse counting 
Entry  Thu Jan 19 23:26:26 2012, Heejong Kim, drs_exam.cpp for evaluation board version 4 
    Reply  Fri Jan 20 08:09:38 2012, Stefan Ritt, drs_exam.cpp for evaluation board version 4 drs_exam.cpp
       Reply  Fri Jan 20 23:50:39 2012, Heejong Kim, drs_exam.cpp for evaluation board version 4 
Entry  Wed Dec 14 00:44:37 2011, Hao Huan, Synchronization Delay in the Firmware for 8051 Controller 
    Reply  Wed Dec 14 08:55:29 2011, Stefan Ritt, Synchronization Delay in the Firmware for 8051 Controller 
Entry  Mon Dec 12 16:43:04 2011, Stefan Ritt, DC coupled DRS4 input stage DRS4_front_end_DC.pdf
Entry  Thu Apr 14 18:23:53 2011, Bob Hirosky, Fixes to DOScreen.cpp for recent built on linux 
    Reply  Fri Apr 15 08:28:54 2011, Stefan Ritt, Fixes to DOScreen.cpp for recent built on linux 
    Reply  Fri Dec 9 17:45:48 2011, Michael Bker, Fixes to DOScreen.cpp for recent built on linux 
Entry  Mon Oct 31 09:15:02 2011, Zhongwei Du, How to link PMT 
    Reply  Tue Nov 1 11:07:02 2011, Stefan Ritt, How to link PMT 
Entry  Sun Oct 23 23:32:28 2011, Hao Huan, Phase Shift for ADC Readout 
    Reply  Mon Oct 24 10:30:15 2011, Stefan Ritt, Phase Shift for ADC Readout 
Entry  Sat Oct 15 04:45:25 2011, Aurelien Bouvier, DRS4 eval board: readout rate 
    Reply  Sat Oct 22 00:40:02 2011, Stefan Ritt, DRS4 eval board: readout rate 
Entry  Fri Sep 16 22:06:07 2011, Andriy Zatserklyaniy, compilation error for version 4.0.0 on linux 
    Reply  Mon Sep 19 08:53:22 2011, Stefan Ritt, compilation error for version 4.0.0 on linux 
Entry  Wed Sep 7 16:45:17 2011, Guillaume Blanchard, DRS4 and AD9222 
    Reply  Wed Sep 7 16:56:43 2011, Stefan Ritt, DRS4 and AD9222 
    Reply  Wed Sep 7 17:28:25 2011, Hannes Friederich, DRS4 and AD9222 
       Reply  Fri Sep 9 09:28:57 2011, Guillaume Blanchard, DRS4 and AD9222 
          Reply  Fri Sep 9 09:31:33 2011, Stefan Ritt, DRS4 and AD9222 
Entry  Mon Jul 19 12:07:04 2010, Jinhong Wang, Fixed Patter Timing Jitter 
    Reply  Mon Jul 19 12:47:17 2010, Stefan Ritt, Fixed Patter Timing Jitter Capture.png
       Reply  Mon Jul 4 05:06:00 2011, Jinhong Wang, Fixed Patter Timing Jitter hist_stoppos.jpg
          Reply  Tue Jul 5 10:09:43 2011, Stefan Ritt, Fixed Patter Timing Jitter nonlinearity.png
             Reply  Tue Jul 12 09:49:08 2011, Jinhong Wang, Fixed Patter Timing Jitter 131MHz.jpg
                Reply  Wed Jul 13 04:26:52 2011, Stefan Ritt, Fixed Patter Timing Jitter 
Entry  Wed Jun 1 09:57:43 2011, Martin Petriska, Removing spikes 
    Reply  Thu Jun 2 21:01:29 2011, Stefan Ritt, Removing spikes 
Entry  Fri Feb 25 10:13:51 2011, Stefan Ritt, Announcement digital pulse processing workshop 
Entry  Sat Feb 19 17:25:29 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards 
    Reply  Sat Feb 19 22:46:35 2011, Stefan Ritt, how to synchronize Sampling frequency of two evaluation boards 
       Reply  Mon Feb 21 08:10:31 2011, Stefan Ritt, how to synchronize Sampling frequency of two evaluation boards 
          Reply  Mon Feb 21 12:42:33 2011, S S Upadhya, how to synchronize Sampling frequency of two evaluation boards 
Entry  Tue May 18 09:24:02 2010, Stefan Ritt, Reference design for DRS4 active input buffer ac.pngac_bw.pngdc.pngdc_bw.pngDRS4_ft_V3.jpg
    Reply  Tue Oct 12 03:53:37 2010, Jinhong Wang, Reference design for DRS4 active input buffer 
       Reply  Tue Nov 16 16:38:06 2010, Stefan Ritt, Reference design for DRS4 active input buffer 
Entry  Wed Jul 21 10:46:32 2010, Jinhong Wang, ENOB of DRS 
    Reply  Wed Jul 21 10:58:20 2010, Stefan Ritt, ENOB of DRS 
Entry  Mon Jul 12 16:07:37 2010, Stefan Ritt, Announcement evaluation board V3 eval3.png
Entry  Tue Jun 22 10:50:19 2010, Jinhong Wang, Reset of DRS4 
    Reply  Tue Jun 22 11:02:30 2010, Stefan Ritt, Reset of DRS4 
       Reply  Tue Jun 22 11:29:26 2010, Jinhong Wang, Reset of DRS4 
          Reply  Tue Jun 22 11:35:18 2010, Stefan Ritt, Reset of DRS4 
             Reply  Tue Jun 22 11:37:42 2010, Jinhong Wang, Reset of DRS4 
Entry  Thu May 13 19:14:27 2010, Hao Huan, DVDD Problem of DRS 4 
    Reply  Fri May 14 08:40:14 2010, Stefan Ritt, DVDD Problem of DRS 4 
       Reply  Tue May 18 01:47:59 2010, Hao Huan, DVDD Problem of DRS 4 
          Reply  Tue May 18 08:23:07 2010, Stefan Ritt, DVDD Problem of DRS 4 
             Reply  Wed May 19 02:24:12 2010, Hao Huan, DVDD Problem of DRS 4 
                Reply  Wed May 19 09:16:02 2010, Stefan Ritt, DVDD Problem of DRS 4 
                   Reply  Fri Jun 18 11:31:20 2010, Jinhong Wang, DVDD Problem of DRS 4 
                      Reply  Fri Jun 18 11:45:18 2010, Stefan Ritt, DVDD Problem of DRS 4 
                         Reply  Sat Jun 19 10:09:18 2010, Jinhong Wang, DVDD Problem of DRS 4 
Entry  Wed May 26 19:18:09 2010, Hao Huan, High Frequency Input for DRS 
    Reply  Tue Jun 1 13:36:18 2010, Stefan Ritt, High Frequency Input for DRS 
Entry  Sun May 2 18:36:14 2010, Ignacio Diguez Estremera, DRS4 chip model 
    Reply  Mon May 3 11:09:12 2010, Stefan Ritt, DRS4 chip model 
       Reply  Mon May 3 17:06:02 2010, Ignacio Diguez Estremera, DRS4 chip model 
          Reply  Mon May 3 17:10:29 2010, Stefan Ritt, DRS4 chip model 
             Reply  Mon May 3 23:21:55 2010, Ignacio Diguez Estremera, DRS4 chip model 
                Reply  Tue May 4 11:26:21 2010, Stefan Ritt, DRS4 chip model DRS4_S-Parameter.pdf
                   Reply  Tue May 4 16:23:16 2010, Ignacio Diguez Estremera, DRS4 chip model 
                   Reply  Wed May 12 11:47:39 2010, Jinhong Wang, DRS4 chip model 
                      Reply  Wed May 12 16:26:12 2010, Stefan Ritt, DRS4 chip model 
Entry  Wed May 5 22:30:50 2010, Ignacio Diguez Estremera, Random noise spec in datasheet 
    Reply  Thu May 6 08:15:39 2010, Stefan Ritt, Random noise spec in datasheet 
Entry  Tue Mar 30 22:57:34 2010, Hao Huan, ROFS Configuration 
    Reply  Thu Apr 15 13:48:40 2010, Stefan Ritt, ROFS Configuration 
Entry  Mon Apr 5 17:50:39 2010, Heejong Kim, version 1.2 evaluation board with firmware 13279? 
    Reply  Wed Apr 14 16:34:28 2010, Stefan Ritt, version 1.2 evaluation board with firmware 13279? 
Entry  Tue Apr 28 11:44:07 2009, Stefan Ritt, Simple example application to read a DRS evaluation board drs_exam.cpp
    Reply  Wed Apr 29 07:57:33 2009, Stefan Ritt, Simple example application to read a DRS evaluation board DRS.cppDRS.h
    Reply  Mon Apr 5 17:57:41 2010, Heejong Kim, Simple example application to read a DRS evaluation board 
       Reply  Tue Apr 13 14:15:16 2010, Stefan Ritt, Simple example application to read a DRS evaluation board 
Entry  Fri Apr 9 17:14:45 2010, Hao Huan, Baseline Variation In Data 
    Reply  Tue Apr 13 13:56:07 2010, Stefan Ritt, Baseline Variation In Data 
Entry  Tue Apr 13 10:45:18 2010, lorenzo neri, evaluation board used like a counter 
    Reply  Tue Apr 13 13:12:43 2010, Stefan Ritt, evaluation board used like a counter 
Entry  Sun Mar 21 02:03:44 2010, Hao Huan, PLL Loop Filter Configuration 
    Reply  Mon Mar 22 09:12:19 2010, Stefan Ritt, PLL Loop Filter Configuration 
Entry  Tue Mar 9 23:28:45 2010, Hao Huan, Serial Interface Frequency of the DRS Chip 
    Reply  Wed Mar 10 10:07:28 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip 
       Reply  Thu Mar 18 21:38:10 2010, Hao Huan, Serial Interface Frequency of the DRS Chip 
          Reply  Thu Mar 18 22:10:41 2010, Stefan Ritt, Serial Interface Frequency of the DRS Chip 
Entry  Thu Mar 11 21:37:32 2010, Hao Huan, Input Bandwidth of the DRS Chip 
    Reply  Fri Mar 12 08:04:44 2010, Stefan Ritt, Input Bandwidth of the DRS Chip 
Entry  Thu Mar 4 19:14:10 2010, Hao Huan, Readout of DRS Data 
    Reply  Fri Mar 5 23:29:04 2010, Hao Huan, Readout of DRS Data 
    Reply  Thu Mar 11 11:45:52 2010, Stefan Ritt, Readout of DRS Data 
Entry  Wed Mar 3 17:36:31 2010, Hao Huan, Initialization of the Domino Circuit 
    Reply  Wed Mar 3 17:49:30 2010, Stefan Ritt, Initialization of the Domino Circuit 
Entry  Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4 
    Reply  Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4 start_1ghz.png
       Reply  Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4 
          Reply  Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4 
             Reply  Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4 
                Reply  Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4 
                   Reply  Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4 
                      Reply  Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4 
Entry  Sun Feb 21 13:41:35 2010, Stefan Ritt, Real Time Conference 2010 
Entry  Mon Feb 15 19:43:34 2010, Ron Grazioso, Problem reading oscilloscope binary waveform output test_pulse.pngpulse_IDL.png
    Reply  Tue Feb 16 09:38:59 2010, Stefan Ritt, Problem reading oscilloscope binary waveform output 
Entry  Wed Feb 10 02:57:55 2010, pepe sanchez lopez, Hello 
    Reply  Wed Feb 10 15:35:09 2010, Stefan Ritt, Hello 
Entry  Sun Jan 31 23:52:15 2010, Hao Huan, Failure In Flashing Xilinx PROM 
    Reply  Mon Feb 1 08:30:42 2010, Stefan Ritt, Failure In Flashing Xilinx PROM DRS.cppDRS.hdrs4_eval1.mcs
Entry  Wed Dec 30 14:28:33 2009, aliyilmaz, normal_mode_in_drs_exam.cpp 
    Reply  Mon Jan 11 16:32:21 2010, Stefan Ritt, normal_mode_in_drs_exam.cpp 
Entry  Mon Dec 14 10:14:16 2009, Jinhong Wang, Trigger of DRS4 
    Reply  Tue Dec 15 14:38:09 2009, Stefan Ritt, Trigger of DRS4 
       Reply  Mon Dec 21 10:17:05 2009, Jinhong Wang, Trigger of DRS4 
          Reply  Mon Dec 21 16:52:08 2009, Stefan Ritt, Trigger of DRS4 
             Reply  Tue Dec 22 01:30:55 2009, Jinhong Wang, Trigger of DRS4 
                Reply  Tue Dec 22 09:07:27 2009, Stefan Ritt, Trigger of DRS4 
Entry  Fri Oct 30 03:31:54 2009, Jinhong Wang, outline dimension of DRS4 QFN_package.jpg
    Reply  Wed Nov 4 14:42:22 2009, Stefan Ritt, outline dimension of DRS4 qfn76.png
Entry  Mon Oct 19 11:26:29 2009, Jinhong Wang, output common mode voltage of DRS4 
    Reply  Mon Oct 19 12:46:12 2009, Stefan Ritt, output common mode voltage of DRS4 
Entry  Mon Oct 19 09:06:43 2009, Jinhong Wang, BIAS Pin of DRS4 
    Reply  Mon Oct 19 09:13:00 2009, Stefan Ritt, BIAS Pin of DRS4 
Entry  Fri Oct 16 09:51:03 2009, Jinhong Wang, DSR4 Full Readout Mode 
    Reply  Fri Oct 16 10:16:10 2009, Stefan Ritt, DSR4 Full Readout Mode 
Entry  Wed Oct 14 23:53:05 2009, Armin Kolb, DRS_exam using USB Evaluation Board with OS X Makefile
Entry  Wed Oct 7 17:58:20 2009, Stefan Ritt, VDD switch off speed no_res.png100ohm.png
Entry  Tue Oct 6 11:20:39 2009, Stefan Ritt, VDD instability vdd_no_cap.pngvdd_470uf.png
Entry  Thu Jul 9 09:11:03 2009, Stefan Ritt, Current problems with drs_exam.cpp 
Entry  Tue Jul 7 16:39:57 2009, Stefan Ritt, Power up problem and remedy typical_mode.gif
Entry  Wed Jun 10 12:46:43 2009, Stefan Ritt, Input range switch added in Version 2.1.3 Capture.png
Entry  Mon Apr 27 15:09:49 2009, Stefan Ritt, Amplitude and Timing calibration for DRS4 Evaluation Board uncal.pngcal.png
Entry  Mon Feb 23 09:24:24 2009, Stefan Ritt, Rise-time measurements image001.jpgimage003.jpgsingle.jpg
Entry  Wed Feb 11 12:21:07 2009, Stefan Ritt, Corrected datasheet Rev. 0.8 
Entry  Wed Jan 14 12:02:04 2009, Stefan Ritt, External Trigger Input requirements tap.jpg
    Reply  Wed Jan 14 13:41:44 2009, Stefan Ritt, External Trigger Input requirements 
Entry  Mon Dec 15 13:37:38 2008, Stefan Ritt, Welcome 
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