DRS4 Forum
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Entry  Tue Feb 27 16:34:26 2018, Steven Block, DRS4 Dead times 6x
    Reply  Tue Feb 27 17:04:12 2018, Stefan Ritt, DRS4 Dead times 
       Reply  Tue Feb 27 18:04:18 2018, Steven Block, DRS4 Dead times 
          Reply  Tue Feb 27 18:12:32 2018, Stefan Ritt, DRS4 Dead times 
Entry  Thu Jan 25 05:24:05 2018, chen wenjun, problem with the drscl(drs507) 
    Reply  Thu Jan 25 08:00:16 2018, Stefan Ritt, problem with the drscl(drs507) 
       Reply  Thu Jan 25 08:07:32 2018, chen wenjun, problem with the drscl(drs507) 
Entry  Tue Mar 28 21:53:12 2017, Jim Freeman, drscl doesn't find eval board but drsosc does (Windows 7) 
    Reply  Wed Apr 5 12:28:28 2017, Stefan Ritt, drscl doesn't find eval board but drsosc does (Windows 7) Screen_Shot_2017-04-05_at_12.27.46_.pngScreen_Shot_2017-04-05_at_11.45.07_.png
    Reply  Thu Jan 25 06:10:52 2018, chen wenjun, drscl doesn't find eval board but drsosc does (Windows 7) 
Entry  Wed Jan 17 09:51:16 2018, Tran Cong Thien, The input signals recorded are different with the signal showed in oscilloscope  
    Reply  Wed Jan 17 10:09:09 2018, Stefan Ritt, The input signals recorded are different with the signal showed in oscilloscope  
Entry  Tue Mar 26 01:17:59 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp 
    Reply  Thu Apr 4 11:32:21 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
       Reply  Fri Apr 5 02:21:33 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp 
          Reply  Fri Apr 5 08:54:37 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp Screen_Shot_2013-04-05_at_8.51.53_.png
             Reply  Wed Apr 10 22:41:21 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp 
                Reply  Thu Apr 11 08:39:12 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
                   Reply  Thu Apr 11 23:32:57 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp 
                      Reply  Fri Apr 12 08:25:05 2013, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
                         Reply  Wed Dec 20 15:30:38 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp 
                            Reply  Wed Dec 20 16:21:42 2017, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
                               Reply  Wed Dec 20 16:30:45 2017, Yoni Sher, cascading -- DRS4 Osci.cpp & DRS.cpp 
                                  Reply  Wed Dec 20 22:14:35 2017, Stefan Ritt, cascading -- DRS4 Osci.cpp & DRS.cpp 
Entry  Tue Dec 12 00:25:50 2017, Diego Yankelevich, External trigger using Raspberry Pi 
    Reply  Tue Dec 12 13:58:06 2017, Stefan Ritt, External trigger using Raspberry Pi 
Entry  Thu Nov 16 02:55:44 2017, Diego Yankelevich, Averaging capabilities  
    Reply  Wed Nov 22 14:52:31 2017, Stefan Ritt, Averaging capabilities  
Entry  Wed Nov 22 08:31:03 2017, chen wenjun , using of the DRS Command Line Interface ΢ͼƬ_20171122153834.png
    Reply  Wed Nov 22 08:48:36 2017, Stefan Ritt, using of the DRS Command Line Interface 
       Reply  Wed Nov 22 08:58:33 2017, chen wenjun , using of the DRS Command Line Interface ΢ͼƬ_20171122160245.png
          Reply  Wed Nov 22 09:14:18 2017, Stefan Ritt, using of the DRS Command Line Interface 
             Reply  Wed Nov 22 09:19:11 2017, chen wenjun , using of the DRS Command Line Interface 
Entry  Fri Nov 3 12:11:14 2017, Hkan Wennlf, Triggering using AND 
    Reply  Fri Nov 3 13:28:04 2017, Stefan Ritt, Triggering using AND 
Entry  Tue Oct 17 14:58:58 2017, Vadym Denysenko, Time offset  
    Reply  Wed Oct 18 09:12:26 2017, Stefan Ritt, Time offset  
       Reply  Wed Oct 18 11:48:14 2017, Vadym Denysenko, Time offset  
Entry  Fri Oct 13 03:39:01 2017, Jonathan Wapman, Raspberry Pi Connection Failure 
    Reply  Mon Oct 16 15:35:22 2017, Stefan Ritt, Raspberry Pi Connection Failure 
Entry  Wed Sep 27 16:11:03 2017, Yoni Sher, Event acquisition pace for irregular timing 
    Reply  Mon Oct 2 16:08:05 2017, Stefan Ritt, Event acquisition pace for irregular timing 
Entry  Sun Aug 27 12:44:16 2017, Yuvaraj Elangovan, DRS4 version Support 
Entry  Fri Jul 21 09:16:02 2017, Volodymyr Rodin, Time output 
    Reply  Tue Jul 25 14:47:05 2017, Volodymyr Rodin, Time output 
Entry  Fri Jun 16 17:34:20 2017, Laura Gonella, Driver installation on Windows 10 
    Reply  Thu Jul 20 13:00:44 2017, Volodymyr Rodin, Driver installation on Windows 10 
Entry  Wed Jul 12 04:24:39 2017, Toshihiro Nonaka, Time resolution between boards 
    Reply  Wed Jul 12 20:16:05 2017, Stefan Ritt, Time resolution between boards 
Entry  Thu Jul 6 15:10:48 2017, Esperienza Giove, Trigger setting (AND AND) OR (AND AND) 
    Reply  Fri Jul 7 10:31:47 2017, Stefan Ritt, Trigger setting (AND AND) OR (AND AND) 
Entry  Thu Jun 8 14:26:23 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels 
    Reply  Thu Jun 8 15:52:20 2017, Stefan Ritt, AND Trigger problems with 2-3 channels 
       Reply  Fri Jun 9 09:44:33 2017, Rebecca Schmitz, AND Trigger problems with 2-3 channels Screenshot1.pngScreenshot2.pngScreenshot3.png
          Reply  Thu Jun 22 21:36:08 2017, Stefan Ritt, AND Trigger problems with 2-3 channels 
Entry  Tue May 30 20:45:30 2017, Esperienza Giove, Setting input range 
    Reply  Tue May 30 21:00:26 2017, Stefan Ritt, Setting input range 
       Reply  Tue May 30 21:22:10 2017, Esperienza Giove, Setting input range 
Entry  Mon May 22 18:27:56 2017, Esperienza Giove, Invalid magic number 0000 
    Reply  Tue May 23 10:24:47 2017, Stefan Ritt, Invalid magic number 0000 
       Reply  Thu May 25 20:17:41 2017, Esperienza Giove, Invalid magic number 0000 
          Reply  Fri May 26 08:48:25 2017, Stefan Ritt, Invalid magic number 0000 
       Reply  Thu May 25 20:20:57 2017, Esperienza Giove, Invalid magic number 0000 
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