 Thu Jul 18 01:03:44 2019, Ismael Garcia, Trace Impedance 
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Hi Steffan,
I'm an engineer at UCLA developing a board with the DRS4 chip. Our team has a question on |
 Thu Jul 18 11:37:56 2019, Stefan Ritt, Trace Impedance
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The requiremnet is the same as for any high speed analog board, there is othing special with the DRS4. If you want to terminate your line with 50 Ohms
and you want a matched impedance layout, you route all lines with 50 Ohms impedance. Truth is however that nothing is perfect. The SMA connector is not
exactly 50 Ohm, the PCB gets a 10-20% variation depending on the manufacturer. So even if you try hard, you will never have a 50 Ohm matched impedance. |
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Fri Jul 19 01:37:09 2019, Ismael Garcia, Trace Impedance
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When you're refering to laying a 50 Ohm trace, you're referring to the SMA input and not the interface between the output of the Op-AMP(THS4508)
buffer
and the inputs of the DRS4(IN0-IN8). Is there a recommended diffential impedance for IN0-IN8? |
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Sat Jul 20 12:28:14 2019, Stefan Ritt, Trace Impedance
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The DRS4 input is high impedance. So if you like you can terminate it with 100 Ohm differentially and route it with 100 Ohm. But if you keep the lines
short, the reflection is negligible. That’s what we made on the evaluation board.
Ismael |
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Sat Jul 13 01:00:15 2019, Brendan Posehn, Evaluation Board Test Functionality
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Hello,
I have recently obtained a DRS4 Evaluation Board (V5), but I am unable to register signals when using the DRS Oscilloscope application. There
seems to be some difference in noise when I have an input connected to a signal or not, but I am unable to view a simple, 0.2V amplitude square wave or |
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Mon Jul 15 17:26:50 2019, Stefan Ritt, Evaluation Board Test Functionality
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Have you set the trigger correctly to the channel with your signal, polarity and level? Do you undersand the difference between normal and auto trigger?
Why don't you post a screendump. Are you ABSOLUTELY SURE that you have a signal on your cable? Have you tried with another oscilloscope? Are you sure
that your SMA connector is good? |
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Mon Jul 15 19:34:25 2019, Brendan Posehn, Evaluation Board Test Functionality
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Hello Stefan,
Thanks for the quick reply. The issue was a faulty SMA connector, should have checked this first. Signal looks good now.
Thanks for your time, |
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Tue Jun 25 23:04:29 2019, Si Xie, drs_exam is always reading out a sin wave
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We are using the drs_exam.cpp to read out waveforms, but it seems to be outputting only sin waves on all channels - as if it was reading out the simulated
waveform from the oscilloscope program if we run it without the board plugged in. Does anyone know what is causing this?
We are taking data with a pulser plugged into channel 1, which produces a single pulse with width of 8ns, and nothing plugged into channel |
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Wed Jun 26 13:08:42 2019, Stefan Ritt, drs_exam is always reading out a sin wave
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Sure, that’s correct. The example program turns on the internal sine wave generator in case people don’t have a real signal. That’s
why it’s called „example“. Find the code which turns on the generator and change it. You will also have to change the trigger settings
depending on your actual signal. |
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Wed Jun 26 15:10:09 2019, Si Xie, drs_exam is always reading out a sin wave
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I see. Where is the code that we can use to turn off the generator? I thought the example is taking data with CH1 as the trigger.
For our board, which is BoardType == 9, it is running these lines:
b->EnableTrigger(1, 0); // enable hardware trigger |
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Mon Jul 8 14:29:12 2019, Stefan Ritt, drs_exam is always reading out a sin wave
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Actually in the original drs_exam.cpp the sine wave oscillator is turned off with this command
/* use following line to turn on the internal 100 MHz clock connected to all channels */
//b->EnableTcal(1); |
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Wed Mar 7 22:49:38 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp
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Hello,
We have been using the DRS4 evaluation board (S/N 2636) that works with the scope application. However we are trying to run the DRS4 evaluation
board remotely by modifying the drs_exam.cpp to acquire and store data continuously. |
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Thu Mar 8 22:54:20 2018, Rodrigo Trindade de Menezes, Running drs_example.cpp
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We found a way to solve the previous problem, but right now when we try to set the input range only -0.5 to 0.5 is working. When we set the function
"SetInputRange(0.5)" for 0 to 1V the output is all zeros and with "SetInputRange(0.45)" we just get all the outputs -49.9mV.
What does that means? How to fix? |
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Fri May 4 12:11:57 2018, Stefan Ritt, Running drs_example.cpp
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And here is the second part of your answer: When you change the input range, you have to redo the voltage calibration. Best is if you do that in the
DRSOsc program, then you see that it's working. Then start your custom program and use the same range.
Stefan |
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Wed Jun 26 15:17:51 2019, Si Xie, Running drs_example.cpp
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Hi Rodrigo, I'm wondering how you solved your original triggering problem. We are also having trouble with collecting data continously using the
example. Thanks.
Rodrigo |
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Mon Mar 19 15:12:02 2018, Stefan Ritt, Running drs_example.cpp
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The time channel is already calibrated in ns. So for 5 GSPS, the time scale goes from zero to 200. Concerning your other issues I will come back to you
later.
Stefan |
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Thu Jun 20 01:36:48 2019, Andrew Peck, Evaluation firmware wait_vdd state
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Dear Stefan,
I am working with others at UCLA on a custom made board built around the DRS4. We are in the process of writing firmware so I am adapting the
readout state machine from the evaluation board firmware. |
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Fri Jun 21 12:54:47 2019, Stefan Ritt, Evaluation firmware wait_vdd state
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Dear Andrew,
the posting you mention is still accurate. Any power supply will drop when you start the Domino wave, no matter how big your capacitor is. Unfortunately
the output signal of the DRS4 scales with VDD. So if your VDD drops by 40 mV and you get a trigger and you immediately start the readout, the output baseline |
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Mon Jun 24 23:07:35 2019, Andrew Peck, Evaluation firmware wait_vdd state
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Dear Stefan,
Thanks so much for clarifying this. We made wait_vdd a parameter controlled by software and will try to experiment with it to find some compromise
between deadtime and the offset added by the droop in VDD. |
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Fri Apr 12 09:39:30 2019, Lev Pavlov, multi-board
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Good afternoon, I use 5 boards in multi-mode, everything is connected according to the instructions. Can I measure the phase difference between
the two signals on channel 1 and channel 20? with each board the phase shift is added +16 ns I can not figure out how to compensate for this. give thanks |
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Fri Apr 12 09:55:50 2019, Stefan Ritt, multi-board
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Subtract 16 ns from your measured value ;-)
Stefan
Lev |
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Fri Apr 12 09:59:15 2019, Lev Pavlov, multi-board
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I understand this, thanks. But my Chief does not understand this, he wants to see the phase difference without “crutches”. And what
is meant in the manual 50 ps resolution? Maybe I just do not understand something? And if you submit a reference signal not in the mode of a garland, but |
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Fri Apr 12 12:50:18 2019, Stefan Ritt, multi-board
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If you have two signal going through two cables, the cable have never the same length (on a scale of picoseconds), and you have to calibrate that anyway.
So a proper timing calibration is not a crutch.
What do you mean by "manual 50ps"? The manual does not mention any resolution. In my experience, you can achieve about 10ps between |
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Thu Mar 14 03:43:49 2019, Deepak Samuel, How to buy DRS evaluation kit
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Dear Stefan,
I have emailed drs4@psi.ch a couple of times regarding the pricing of the evaluation kits for academic use in India and have not received any
reply and hence writing in this forum. Could you please help me in this? |
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Fri Mar 8 19:35:11 2019, Abaz Kryemadhi, ROOT Macro for newest software
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The older root macro did not work for me for data acquired with the newest software.
so for the newest software and multiple boards, I modified the read_binary.cpp into read_binary.C for those who like to use the root macro, see
the attachment. |
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Wed Mar 6 10:09:01 2019, Willy Chang, drscl "no board found" in some Win7 or Win8.X PCs
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Hi all,
When connecting the board and running the Zadig program, some Windows PCs may return "driver installation failed." I coudn't
find the solution from their download website. So I started the drscl first. Apparently it shows: Successfully scanned, but |
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Mon Feb 4 16:42:08 2019, Hans Steiger, Different Distances between the sampling points
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Dear All,
with the older software for my V5 Board i did not have the problem, that the distance between the sampling points (in time) is not the same (e.g.
a sampling point all 200ps for 5GS/s). |
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Mon Feb 4 16:46:04 2019, Stefan Ritt, Different Distances between the sampling points
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The sampling points are NOT equidestant, they have varying bin widths of 150ps to 250ps at 5GS/s. That's due the way the DRS4 chip works. You might
have neglected that fact in the past, but that would have led to poor timing resolutions (typically 1-2ns resolution only). To get bins with the same width,
you have to treat your waveform as a real X/Y points (or better U/T), and the re-sample that cure, maybe spline-interpolated, at 200ps bins. |
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Mon Feb 4 17:36:49 2019, Hans Steiger, Different Distances between the sampling points
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Sorry.... but is there a solution or a Root Macro, that reads the waveforms into a Root-Tree? I simply can not work anymore with the data.
Can you tell me, which software was in use in early 2017?
All the best, |
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Mon Feb 4 18:18:22 2019, Stefan Ritt, Different Distances between the sampling points
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elog:361
Hans
Steiger wrote:
Sorry.... but is there a solution or a Root Macro, that reads the |
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Sat Feb 2 00:13:12 2019, Hans Steiger, Saving Rate (only 15Acq/s)
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Dear All,
when I use my Evaluation Board with some PMTs I can digitize 450 Acq/s or so. But when I want to save the waveforms the rate goes down. The Acqu. |
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Sat Feb 2 10:10:22 2019, Stefan Ritt, Saving Rate (only 15Acq/s)
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The reduction of rate is because you save in XML format, which is an ASCII format, so human readable, but takes long to write. If you switch to binary
format and write on a decent fast hard disk, you should get back to 450 Acq/s.
Stefan |
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Tue Jan 29 14:43:44 2019, Abaz Kryemadhi, ROOT Macro for data acquired with the newest software
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Hello,
Is there a root macro for decoding binary data acquired with the newest software for single board or multi-boards daisy chained?
Cheers, |
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Wed Jan 30 17:08:58 2019, Stefan Ritt, ROOT Macro for data acquired with the newest software
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This one elog:361 should still work.
Stefan
Abaz |
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Wed Jan 30 06:51:37 2019, Saurabh Neema, DRS4 domino wave stability study
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We have been using DRS4 IC in our design for quite some time and it is giving good performance.
Till now we were using Domino wave frequency as 1 GSPS by use of reference clock to DRS4 and internal PLL of DRS4. Recently we tried to use 4GSPS
by modifying the reference clock. |
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Wed Jan 30 08:02:25 2019, Stefan Ritt, DRS4 domino wave stability study
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The Domino wave is most stable at 5 GSPS, slowly degrades down to 3-2 GSPS, and at 1GSPS gets some significant jitter. This is for internal reasons in
the chip and cannot be compensated by the loop filter. It is therefore important to run it as fast as possible if you want to achieve best timing resolution.
As a rule of thumb, the jitter at 5 GSPS is about 20-25 ps, and at 1 GSPS it is maybe 150 ps. If you require good timing resolution, you can use the 9th |
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Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue
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Hi,
We are using the DRS4 Evaluation Board as a digitizer in our laboratory.
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Thu Nov 8 11:54:33 2018, Stefan Ritt, Timing Issue
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That's not a bug, but a feature of the DRS4 chip. The time bins have different values by the properties of the chip. They are generated by a chain of inverters,
which all have different propagation times. This delay is measured by the time calibration and then applied. If you want equidistant bins,
you have to interpolate your data points (linearly or by splines) and resample the signal. You can find more details in the DRS4 data sheet.
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Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue
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Thanks a lot for the quick response.
We will do as you suggest.
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Mon Nov 5 17:17:08 2018, Sean Quinn, Pi attenuator on eval board inputs?
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Dear DRS4 team,
I am curious about this part of the circuit: |
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Thu Nov 8 09:57:26 2018, Stefan Ritt, Pi attenuator on eval board inputs?
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The attenuator compensates for the gain of the buffer which is slightly above one. In addition, it serves as a "placeholder" in case one wants
larger input signals. One can easily convert the attenuator to -6db, -12db, etc. by chaning the resistors.
Stefan |
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Sun Sep 23 02:22:46 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms
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Hello Stefan,
I am using the DRS4 board connected to a Raspberry PI and through the drsosc application. I am interested on using the "Trigger OUT"
signal to do some extra data processing with NIM modules. According to the manual, for each hardware trigger a TTL pulse of 150 ns width should be send |
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Wed Sep 26 14:44:14 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms
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The "Trigger OUT" has changed recently. It goes high on a new trigger, but then STAYS high until the board has been read out by the PC and
re-started. This allows better synchronization with some external trigger, which can be re-armed with the falling edge of the trigger out signal. The signal
can be quite long, since readout of an event via USB typically takes 2 ms, but can be more if the PC is busy. If you need back your 150 ns pulse, |
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Wed Sep 26 18:28:20 2018, Gerard Arino-Estrada, Trigger OUT pulse width variable from 100 us up to 100 ms
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Thank you very much for the answer, I really appreciate your help.
Thanks!
Gerard |
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Wed Sep 26 19:21:03 2018, Stefan Ritt, Trigger OUT pulse width variable from 100 us up to 100 ms
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In meantime I even updated the manual.
Stefan
Gerard |
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Thu May 17 13:29:34 2018, Stefan Ritt, "Symmetric spikes" fixed
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Good news for all DRS4 users. After many years, I finally understand where the "symmetric spikes" come from and how to fix them.
The "symmetric spikes" are small spikes of 17-18mV, which randomly happen at 1-2 cells. They alwas come in groups of 2 in each channel,
symmetric around sampling cell #512. See first attachment. |
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Mon Sep 3 11:17:26 2018, Martin Petriska, "Symmetric spikes" fixed
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Hi,
Is it possible to fix it by FPGA changes? I see readout cycle (proc_drs_reedout) in drs4_eval(4)5_app.vhd, but not sure where to exactly
put this three commands. Could you please attach app.vhd file for eval board with example how to fix ? |
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Tue Sep 4 13:04:30 2018, Stefan Ritt, "Symmetric spikes" fixed
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Yes it's possible, but I have to find time for that. The software of the evaluation board takes care of the spikes ("remove spikes"), so
I thought it's not so urgent to fix that in the FPGA (which takes me some time).
Stefan |
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Thu Sep 13 18:09:13 2018, Martin Petriska, "Symmetric spikes" fixed
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Ok, so I made it ... and Yes it works :),
https://youtu.be/0noy4CoFoh8
here is changed part in drs4_eval4_app.vhd |
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Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed
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Dear DRS4 team,
On page 3 of the data sheet, Table 1. for readout speed a typical value of 10 MHz is specified, but in the comment column it notes optimal performance
achieved at 33 MHz. |
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Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed
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The analog output of the DRS4 chip needs some time to settle. In principle it need an infinite amout of time (exponential curve) to settle to 100% of
the final value. So if we sample after a finite time, there is some error we do. Some of the error will be taken care of the voltage calibration, but there
remains some residual error depending on the value of the previous sampling cell. So all sampling speeds 10 MHz, 16 MHz, 33 MHz are kind of rule of thumbs. |
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Mon Aug 13 19:44:59 2018, Martin Petriska, Latch delay support
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Hi,
https://forge.physik.rwth-aachen.de/projects/drs4-rwth
Not sure about their licensing, but is it possible to add latch delay support to official firmware ? |
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Tue Aug 14 06:10:49 2018, Stefan Ritt, Latch delay support
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I put that on the wish list, but I won't have time for that in the next months.
Stefan
Martin |
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Mon Jul 16 19:39:35 2018, Woon-Seng Choong, Effect of interpolation on timing
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Using a test pulse split into two channels of the DRS4 Evaluation Board v5, I looked at the time resolution using a leading edge threshold.
The voltage and timing calibration was performed. One method (1) is to linearly interpolate between two points of the raw waveform that
is above and below the threshold (this is exactly the algorithm given in read_binary.c in the drs4 source distribution); and another (2) is to |
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Fri Jul 20 00:44:13 2018, Woon-Seng Choong, Effect of interpolation on timing
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Just a follow-up update.
It turns out that I was using a cubic spline interpolation with smoothing. If I required the cubic spline to go through the sampled points, then
I obtained similar time resolution as the simple linear interpolation. |